LH28F400SUB-Z0 데이터 시트보기 (PDF) - Sharp Electronics

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LH28F400SUB-Z0

4M (512K × 8, 256K × 16) Flash Memory

Sharp Electronics 

LH28F400SUB-Z0

4M (512K × 8, 256K × 16) Flash Memory

INTRODUCTION

Sharp’s LH28F400SU 4M Flash Memory is a revolu-

tionary architecture which enables the design of truly

mobile, high performance, personal computing and

communication products. With innovative capabilities,

3.3 V low power operation and very high read/write per-

formance, the LH28F400SU is also the ideal choice for

designing embedded mass storage flash memory

systems.

The LH28F400SU’s independently lockable 32 sym-

metrical blocked architecture (16K each) extended

cycling, low power operation, very fast write and read

performance and selective block locking provide a highly

flexible memory component suitable for cellular phone,

facsimile, game, PC, printer and handy terminal. The

LH28F400SU’s 5.0 V/3.3 V power supply operation

enables the design of memory cards which can be read

in 3.3 V system and written in 5.0 V/3.3 V systems. Its

x8/x16 architecture allows the optimization of memory

to processor interface. The flexible block locking option

enables bundling of executable application software in

a Resident Flash Array or memory card. Manufactured

on Sharp’s 0.45 µm ETOX™ process technology, the

LH28F400SU is the most cost-effective, high-density

3.3 V flash memory.

DESCRIPTION

The LH28F400SU is a high performance 4M

(4,194,304 bit) block erasable non-volatile random

access memory organized as either 256K × 16 or

512K × 8. The LH28F400SU includes thirty-two 16K

(16,384) blocks. A chip memory map is shown in

Figure 3.

The implementation of a new architecture, with many

enhanced features, will improve the device operating

characteristics and results in greater product reliability

and ease of use.

Among the significant enhancements of the

LH28F400SU:

• 3 V Read, 5 V Write/Erase Operation

(5 V VPP, 3 V VCC)

• Low Power Capability (2.7 V VCC Read)

• Improved Write Performance

• Dedicated Block Write/Erase Protection

• Command-Controlled Memory Protection

Set/Reset Capability

The LH28F400SU will be available in a 49-pin,

.67 mm thick × 8 mm × 8 mm CSP package. This form

factor and pinout allow for very high board layout densi-

ties.

A Command User Interface (CUI) serves as the sys-

tem interface between the microprocessor or

microcontroller and the internal memory operation.

Internal Algorithm Automation allows Byte Writes and

Block Erase operations to be executed using a Two-

Write command sequence to the CUI in the same way

as the LH28F008SA 8M Flash memory.

A Superset of commands have been added to the

basic LH28F008SA command-set to achieve higher

write performance and provide additional capabilities.

These new commands and features include:

• Software Locking of Memory Blocks

• Memory Protection Set/Reset Capability

• Two-Byte Serial Writes in 8-bit Systems

• Erase All Unlocked Blocks

Writing of memory data is performed typically within

20 µs per byte. Writing of memory data is performed

typically within 30 µs per word. A Block Erase operation

erases one of the 32 blocks in typically 0.8 seconds,

independent of the other blocks.

LH28F400SU allows to erase all unlocked blocks. It

is desirable in case of which you have to implement

Erase operation maximum 32 times.

LH28F400SU enables Two-Byte serial Write which

is operated by three times command input. Writing of

memory data is performed typically within 30 µs per

two-byte. This feature can improve 8-bit system write

performance by up to typically 15 µs per byte.

All operations are started by a sequence of Write

commands to the device. Status Register (described in

detail later) and a RY »/BY » output pin provide informa-

tion on the progress of the requested operation.

Same as the LH28F008SA, LH28F400SU requires

an operation to complete before the next operation can

be requested, also it allows to suspend block erase to

read data from any other block, and allow to resume

erase operation.

The LH28F400SU provides user-selectable block

locking to protect code or data such as Device Drivers,

PCMCIA card information, ROM-Executable OS or

Application Code. Each block has an associated non-

volatile lock-bit which determines the lock status of the

block. In addition, the LH28F400SU has a software con-

trolled master Write Protect circuit which prevents any

modifications to memory blocks whose lock-bits are set.

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