MT4LC4M16F5TG-5 데이터 시트보기 (PDF) - Micron Technology

부품명

상세내역

제조사

MT4LC4M16F5TG-5

4 MEG x 16 FPM DRAM

Micron Technology 

NOTES (continued)

30. Last rising CASx# edge to next cycle’s last rising

CASx# edge.

31. Last rising CASx# edge to first falling CASx#

edge.

32. First DQs controlled by the first CASx# to go

LOW.

33. Last DQs controlled by the last CASx# to go

HIGH.

4 MEG x 16

FPM DRAM

34. Each CASx# must meet minimum pulse width.

35. Last CASx# to go LOW.

36. All DQs controlled, regardless CASL# and CASH#.

37. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse

width £ 3ns, and the pulse width cannot be

greater than one third of the cycle rate. VIL

undershoot: VIL (MIN) = -2V for a pulse width £

3ns, and the pulse width cannot be greater than

one third of the cycle rate.

4 Meg x 16 FPM DRAM

D28_2.p65 – Rev. 5/00

9

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000, Micron Technology, Inc.

Share Link: