IS24C02D
Figure 4. Data Validity Protocol
SCL
SDA
Data Change
Data Stable
Data Stable
Figure 5. Slave Address
BIT 7
1
65
01
4
3
2
1
0
0 A2 A1 A0 R/W
Normal
Instruction
BIT 7
65
4
3
2
1
0
Permanent Write Protect
0 1 1 0 A2 A1 A0 R/W Instruction
Figure 6. Byte Write
S
T
A
R
T
SDA
Bus
Device
Address
W
R
I
T
E
*
A
C
Word Address *
A
C
Activity
K
K
M
S
L
S
M
S
B
B
B
R/W
Data
S
T
*
O
P
A
C
K
* Acknowledges provided by the slave regardless of hardware or software Write Protection.
Figure 7. Page Write
S
W
T
R
A
R
Device
I
T
T
Address E * Word Address (n) *
Data (n)
*
SDA
A
A
A
Bus
C
C
C
Activity
K
K
K
M
L
S
S
B
B
R/W
Data (n+1)
*
A
C
K
Data (n+15)
S
T
O
*P
A
C
K
* Acknowledges provided by the slave regardless of hardware or software Write Protection.
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
07/27/09