IS24C52-2G 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS24C52-2G

2k-bit 2-WIRE SERIAL CMOS EEPROM with Permanent Write-Protection

Integrated Silicon Solution 

IS24C52

ISSI ®

READ OPERATION

Read operations are initiated in the same manner as Write

operations, except that the (R/W) bit of the Slave address is

set to “1”. There are three Read operation options: current

address read, random address read and sequential read.

Current Address Read

The IS24C52 contains an internal address counter which

maintains the address of the last byte accessed,

incremented by one. For example, if the previous

operation is either a Read or Write operation addressed

to the address location n, the internal address counter

would increment to address location n+1. When the

IS24C52 receives the Device Addressing Byte with a

Read operation (R/W bit set to “1”), it will respond an ACK

and transmit the 8-bit data byte stored at address

location n+1. The Master should not acknowledge the

transfer but should generate a Stop condition so the

IS24C52 discontinues transmission. If 'n' is the last byte

of the memory, then the data from location '0' will be

transmitted. (Refer to Figure 8. Current Address Read

Diagram.)

Random Address Read

Selective Read operations allow the Master device to select

at random any memory location for a Read operation. The

Master device first performs a 'dummy' Write operation by

sending the Start condition, Slave address and word address

of the location it wishes to read. After the IS24C52

acknowledges the word address, the Master device resends

the Start condition and the Slave address, this time with the

R/W bit set to one. The IS24C52 then responds with its ACK

and sends the data requested. The Master device does not

send an ACK but will generate a Stop condition. (Refer to

Figure 9. Random Address Read Diagram.)

Sequential Read

Sequential Reads can be initiated as either a Current

AddressReadorRandomAddressRead. AftertheIS24C52

sends the initial byte sequence, the Master device responds

with an ACK indicating it requires additional data from the

IS24C52. The IS24C52 continues to output data for each

ACK received. The Master device terminates the sequential

Read operation by pulling SDA High (no ACK) indicating the

last data byte to be read, followed by a Stop condition.

The data output is sequential, with the data from address n

followed by the data from address n+1, ... etc. The address

counter increments by one automatically, allowing the

entire memory contents to be serially read during sequential

Read operations. When the memory address boundary 255

is reached, the address counter “rolls over” to address 0, and

the IS24C52 continues to output data for each ACK received.

(Refer to Figure 10. Sequential Read Operation Starting with

a Random Address Read Diagram.)

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

PRELIMINARYINFORMATION Rev. 00B

01/26/04

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