IS25LD256C 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS25LD256C

256Kbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus Interface

Integrated Silicon Solution 

IS25LD256C

SPI MODES DESCRIPTION

Multiple IS25LD256C devices can be connected on the The difference between these two modes is the clock

SPI serial bus and controlled by a SPI Master, i.e.

polarity when the SPI master is in Stand-by mode: the

microcontroller, as shown in Figure 1. The devices

serial clock remains at “0” (SCK = 0) for Mode 0 and

support either of two SPI modes:

the clock remains at “1” (SCK = 1) for Mode 3. Please

Mode 0 (0, 0)

refer to Figure 2. For both modes, the input data is

Mode 3 (1, 1)

latched on the rising edge of Serial Clock (SCK), and

the output data is available from the falling edge of

SCK.

Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)

SPI Interface with

(0,0) or (1,1)

SDIO

SDI

SCK

SPI Master

(i.e. Microcontroller)

CS3 CS2 CS1

SCK SO SIO

SCK SO SIO

SCK SO SIO

SPI Memory

Device

CE# WP#

HOLD#

SPI Memory

Device

CE# WP#

HOLD#

SPI Memory

Device

CE# WP#

HOLD#

Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as

Figure 2. SPI Modes Supported

Integrated Silicon Solution, Inc.- www.issi.com

4

Rev. A

09/11/2012

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