IS61NLP12832B 데이터 시트보기 (PDF) - Integrated Silicon Solution

부품명

상세내역

제조사

IS61NLP12832B

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

Integrated Silicon Solution 

IS61NLP12832B

 IS61NLP12836B/IS61NVP12836B

 IS 61NLP25618A/IS61NVP25618A

ASYNCHRONOUS TRUTH TABLE(1)

Operation

ZZ

OE

I/O STATUS

Sleep Mode

H

X

High-Z

Read

L

L

L

H

DQ

High-Z

Write

L

X

Din, High-Z

Deselected

L

X

High-Z

Notes:

1. X means "Don't Care".

2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data

bus contention will occur.

3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.

4. Deselected means power Sleep Mode where stand-by current depends on cycle time.

WRITE TRUTH TABLE (x18)

Operation

WE

BWa

BWb

READ

H

X

X

WRITE BYTE a

L

L

H

WRITE BYTE b

L

H

L

WRITE ALL BYTEs

L

L

L

WRITE ABORT/NOP

L

H

H

Notes:

1. X means "Don't Care".

2. All inputs in this table must beet setup and hold time around the rising edge of CLK.

Integrated Silicon Solution, Inc. — www.issi.com

11

Rev.  D

09/10/07

Share Link: