IS61NLP12832B 데이터 시트보기 (PDF) - Integrated Silicon Solution
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IS61NLP12832B
Integrated Silicon Solution
IS61NLP12832B Datasheet PDF : 29 Pages
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IS61NLP12832B
IS61NLP12836B/IS61NVP12836B
IS 61NLP25618A/IS61NVP25618A
Pin Configuration — 128K x 36, 165-Ball PBGA (Top View)
1
2
3
4
5
6
7
8
A
NC
B
NC
A
CE
BWc
BWb
CE2
CKE
ADV
A
CE2
BWd
BWa
CLK
WE
OE
C DQPc
NC
Vddq
VSS
VSS
VSS
VSS
VSS
D DQc
DQc
Vddq
Vdd
VSS
VSS
VSS
Vdd
E DQc
DQc
Vddq
Vdd
VSS
VSS
VSS
Vdd
F DQc
DQc
Vddq
Vdd
VSS
VSS
VSS
Vdd
G DQc
DQc
Vddq
Vdd
VSS
VSS
VSS
Vdd
H
NC
NC
NC
Vdd
VSS
VSS
VSS
Vdd
J
DQd
DQd
Vddq
Vdd
VSS
VSS
VSS
Vdd
K DQd
DQd
Vddq
Vdd
VSS
VSS
VSS
Vdd
L DQd
DQd
Vddq
Vdd
VSS
VSS
VSS
Vdd
M DQd
DQd
Vddq
Vdd
VSS
VSS
VSS
Vdd
N DQPd
NC
Vddq
VSS
NC
NC
NC
VSS
P
NC
NC
A
A
NC
A1*
NC
A
R MODE NC
A
A
NC
A0*
NC
A
9
NC
NC
Vddq
Vddq
Vddq
Vddq
Vddq
NC
Vddq
Vddq
Vddq
Vddq
Vddq
A
A
10
11
A
NC
A
NC
NC
DQPb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
NC
ZZ
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
NC
DQPa
A
NC
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
A
Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
WE
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control
Input
CLK
Synchronous Clock
CKE
Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWx (x=a-d) Synchronous Byte Write Inputs
OE
Output Enable
ZZ
Power Sleep Mode
MODE
VDD
NC
DQx
DQPx
VDDQ
Vss
Burst Sequence Selection
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply
3.3V/2.5V
Ground
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
09/10/07
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