ISL24021 데이터 시트보기 (PDF) - Intersil
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ISL24021 Datasheet PDF : 12 Pages
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ISL24021
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD -
TDFN EXPOSED DIEPAD SOLDERED TO PCB
PER JESD51-5
3.0
2.5W
2.5
2.0
TDFN8
θJA = +50 (°C/W)
1.5
1.0
0.5
0
0
25
50
75
100
125
150
AMBIENT TEMP (°C)
FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Printed Circuit Board Layout
As with any high-frequency device, good printed circuit
board layout is necessary for optimum performance. For the
ISL24021 low impedance analog power and ground planes
are recommended, and trace lengths should be as short as
possible. The power supply pins must be well bypassed to
reduce the risk of oscillation. For optimal thermal and
operating performance the ISL24021 thermal pad should
always be connected to the lowest potential, VSS.
For normal single supply operation (the VSS pin is
connected to GND) a 4.7µF capacitor should be placed from
VDD to GND, then a parallel 0.1µF capacitor should be
connected as close to the amplifier as possible. For dual
supply operation the same bypassing techniques should be
utilized by connecting capacitors from each supply to GND.
11
FN6637.0
June 3, 2009
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