59442IB 데이터 시트보기 (PDF) - Intersil
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59442IB Datasheet PDF : 11 Pages
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ISL59442
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified. (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
1.2 1.136W
1
0.8
0.6
θJA =88S°CO/1W4
0.4
0.2
0
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
0.9
0.8
0.7 833mW
0.6
0.5
0.4
0.3
θJA =12S0O°C1/4W
0.2
0.1
0
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Pin Descriptions
PIN NUMBER
1
2, 6, 9
3
4
5
7
8
10
11
PIN NAME
IN0
NIC
IN1
GND
IN2
IN3
V-
OUT
HIZ
12
S1
13
S0
14
V+
IN
CIRCUIT 1.
EQUIVALENT
CIRCUIT
Circuit 1
Circuit 1
Circuit 4
Circuit 1
Circuit 1
Circuit 4
Circuit 3
Circuit 2
Circuit 2
Circuit 2
Circuit 4
DESCRIPTION
Input for channel 0
Not Internally Connected; it is recommended this pin be tied to ground to
minimize crosstalk.
Input for channel 1
Ground pin
Input for channel 2
Input for channel 3
Negative power supply
Output
Output disable (active high); there are internal pull-down resistors, so the
device will be active with no connection; "HI" puts the output in high
impedance state.
Channel selection pin MSB (binary logic code)
Channel selection pin LSB (binary logic code)
Positive power supply
V+
V+
LOGIC PIN
21k
+
33k 1.2V-
GND.
V-
V-
CIRCUIT 2.
V+
OUT
V-
CIRCUIT 3.
V+
GND
V-
CAPACITIVELY
COUPLED
ESD CLAMP
CIRCUIT 4.
7
FN7452.4
January 5, 2007
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