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ISL6406IB

Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

Intersil 

ISL6406, ISL6426

power nodes. Use copper-filled polygons on the top and

bottom circuit layers for the phase nodes. Use the remaining

printed circuit layers for small signal wiring. The wiring traces

from the GATE pins to the MOSFET gates should be kept

short and wide enough to easily handle the 1A of drive

current. The switching components should be placed close

to the ISL6406, ISL6426 first. Minimize the length of the

connections between the input capacitors, CIN, and the

power switches by placing them nearby. Position both the

ceramic and bulk input capacitors as close to the upper

MOSFET drain and islands as possible. Position the output

inductor and output capacitors between the upper and lower

MOSFETs and the load.

The critical small signal components include any bypass

capacitors, feedback components, and compensation

components. Position the bypass capacitor, CBP, close to

the VCC pin with a via directly to the ground plane. Place

the PWM converter compensation components close to the

FB and COMP pins. The feedback resistors for both

regulators should also be located as close as possible to

the relevant FB pin with vias tied straight to the ground

plane as required.

Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

(VOUT) is regulated to the Reference voltage level. The error

amplifier (Error Amp) output (VE/A) is compared with the

oscillator (OSC) triangular wave to provide a pulse-width

modulated (PWM) wave with a peak amplitude of VIN at the

PHASE node. The PWM wave is smoothed by the output

filter (L and CO).The modulator transfer function is the

small-signal transfer function of VOUT/VE/A. This function is

dominated by a DC Gain and the output filter (LO and CO),

with a double pole break frequency at FLC and a zero at

FESR. The DC Gain of the modulator is simply the input

voltage (VIN) divided by the peak-to-peak oscillator voltage,

VOSC.

OSC

PWM

COMPARATOR

∆ VOSC

+-

DRIVER

DRIVER

VIN

LO

PHASE CO

VOUT

ZFB

VE/A

+-

ZIN

ERROR REFERENCE

AMP

ESR

(PARASITIC)

DETAILED COMPENSATION COMPONENTS

C1

C2

R2

ZFB

VOUT

ZIN

C3 R3

COMP

-

+

R1

FB

ISL6406, ISL6426

REFERENCE

FIGURE 7. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

Modulator Break Frequency Equations

fLC

=

--------------1---------------

2Π LOCO

fESR

=

-------------------1---------------------

2Π(ESR)(CO)

The compensation network consists of the error amplifier

(internal to the ISL6406, ISL6426) and the impedance

networks ZIN and ZFB.The goal of the compensation

network is to provide a closed-loop transfer function with the

highest 0dB crossing frequency (f 0dB ) and adequate phase

margin. Phase margin is the difference between the closed

loop phase at f 0dB and 180 degrees.

The equations below relate the compensation network’s

poles, zeros and gain to the components (R1, R2, R3, C1, C2

and C3) in Figure 7. Use these guidelines for locating the

poles and zeros of the compensation network:

1. Pick gain (R2/R1) for desired converter bandwidth.

2. Place first zero below filter’s double pole (~75% FLC).

3. Place second zero at filter’s double pole.

4. Place first pole at the ESR zero.

5. Place second pole at half the switching frequency.

6. Check gain against error amplifier’s open-loop gain.

7. Estimate phase margin—repeat if necessary.

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