ISL8200MIRZ-T(2009) 데이터 시트보기 (PDF) - Intersil
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ISL8200MIRZ-T Datasheet PDF : 23 Pages
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ISL8200M
Pin Descriptions (Continued)
PIN
NUMBER PIN NAME
PIN DESCRIPTION
21
VCC
Analog Input - This pin provides bias power for the analog circuitry. It’s operational range is 2.97V to
5.6V. In 3.3V applications, VCC, PVCC and VIN should be shorted to allow operation at the low end
input as it relates to the VCC falling threshold limit. This pin can be powered either by the internal linear
regulator or by an external voltage source.
22
PGOOD Analog Output - Provides an open drain Power Good signal when the output is within 9% of nominal
output regulation point with 4% hysteresis (13%/9%), and soft-start is complete. PGOOD monitors the
outputs (VMON) of the internal differential amplifiers. Output Voltage Range: 0V to VCC.
23
NC
Not internal connected
PD1
Phase Used for both the PHASE pin (Pin # 16) and for heat removal connecting to heat dissipation layers using
Thermal Pad Vias. Potential should be floating and not electrically connected to anything except PHASE pin 16.
PD2
VIN Thermal Used for both the PVIN pin (Pin # 17) and for heat removal connecting to heat dissipation layers using
Pad
Vias. Potential should be floating and not electrically connected to anything except VPVIN pin 17.
PD3
PGND Used for both the PGND pin (Pin # 18) and for heat removal connecting to heat dissipation layers using
Thermal Pad Vias. Potential should be floating and not electrically connected to anything except PGND pin 18.
PD4
VOUT
Used for both the Vout pin (Pin # 19) and for heat removal connecting to heat dissipation layers using
Thermal Pad Vias. Potential should be floating and not electrically connected to anything except VOUT pin 19.
Typical Application Circuits
J40
VIN1
J41
GND
R76
C65
16.5k
R77
4.12k
U 18
ISL8200M
C73
22uF
PVIN
VIN
FF
C76
1nF
EN
ISFETDRV1
FSY NC_IN
CLKOUT
ISHARE_BUS
ISFETDRV
J38
VOUT1
J39
GND
VOUT
2.2k
C63
R122
VOUT_SET
VSEN _R EM-
PGOOD1
PGOOD
PH_CNTRL
VCC
R I SH AR E7
5k
C75
10uF
FIGURE 3. SINGLE PHASE 10A 1.2V OUTPUT CIRCUIT
5
FN6727.0
December 22, 2009
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