LX64EV-5F100I 데이터 시트보기 (PDF) - Lattice Semiconductor

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LX64EV-5F100I

High Performance Interfacing and Switching

Lattice Semiconductor 

Lattice Semiconductor

ispGDX2 Family Data Sheet

The sysIO interfaces provide system-level performance and integration. These I/Os support various modes of

LVCMOS/LVTTL and support popular high-speed standard interfaces such as GTL+, PCI-X, HSTL, SSTL, LVDS

and Bus-LVDS. The sysHSI Blocks further extend this capability by providing high speed serial data transfer capa-

bility.

Devices in the family can operate at 3.3V, 2.5V or 1.8V core voltages and can be programmed in-system via an

IEEE 1149.1 interface that is compliant with the IEEE 1532 standard. Voltages required for the I/O buffers are inde-

pendent of the core voltage supply. This further enhances the flexibility of this family in system designs.

Typical applications for the ispGDX2 include multi-port multi-processor interfaces, wide data and address bus mul-

tiplexing, programmable control signal routing and programmable bus interfaces. Table 1 shows the members of

the ispGDX2 family and their key features.

Architecture

The ispGDX2 devices consist of GDX Blocks interconnected by a Global Routing Pool (GRP). Signals interface

with the external system via sysIO banks. In addition, each GDX Block is associated with a FIFO and a sysHSI

Block to facilitate the transfer of data on- and off-chip. Figure 1 shows the ispGDX2 block diagram. Each GDX

Block can be individually configured in one of four modes:

• Basic (No FIFO or SERDES)

• FIFO Only

• SERDES Only

• SERDES and FIFO

Each sysIO bank has its own I/O power supply and reference voltage. Designers can use any output standard

within a bank that is compatible with the power supply. Any input standard may be used, providing it is compatible

with the reference voltage. The banks are independent.

Global Routing Pool (GRP)

The ispGDX2 architecture is organized into GDX Blocks, which are connected via a Global Routing Pool. The inno-

vative GRP is optimized for routability, flexibility and speed. All the signals enter via the GDX Block. The block sup-

plies these either directly or in registered form to the GRP. The GRP routes the signals to different blocks, and

provides separate data and control routing. The data path is optimized to achieve faster speed and routing flexibility

for nibble oriented signals. The control routing is optimized to provide high-speed bit oriented routing of control sig-

nals.

There are some restrictions on the allocation of pins for optimal bus routing. These restrictions are considered by

the software in the allocation of pins.

GDX Block

The blocks are organized in a “block” (nibble) manner, with each GDX Block providing data flow and control logic

for 16 I/O buffers. The data flow is organized as four nibbles, each nibble containing four Multiplexer Register

Blocks (MRBs). Data for the MRBs is provided from 64 lines from the GRP. Figure 2 illustrates the groups of signals

going into and out of a GDX Block.

Control signals for the MRBs are provided from the Control Array. The Control Array receives the 32 signals from

the GRP and generates 16 control signals: eight MUX Select, four Clock/Clock Enable, two Set/Reset and two Out-

put Enable. Each nibble is controlled via two MUX select signals. The remaining control signals go to all the MRBs.

Besides the control signals from the Control Array, the following global signals are available to the MRBs in each

GDX Block: four Clock/Clock Enable, one reset/preset, one power-on reset, two of four MUX select (two of two in

64 I/O), four Output Enable (two in 64 I/O) and Test Out Enable (TOE).

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