ISPLSI1016EA 데이터 시트보기 (PDF) - Lattice Semiconductor
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ISPLSI1016EA Datasheet PDF : 13 Pages
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Specifications ispLSI 1016EA
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 4 #2
COND.
DESCRIPTION1
-200
-125
-100
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass — 4.5 — 7.5 — 10.0 ns
tpd2
A 2 Data Propagation Delay, Worst Case Path
— 6.0 — 10.0 — 12.5 ns
fmax (Int.) A 3 Clock Frequency with Internal Feedback 3
200 — 125 — 100 — MHz
fmax (Ext.) —
4
Clock
Frequency
with
External
Feedback
(
1
tsu2 +
) tco1
143
— 100
—
77
— MHz
fmax (Tog.) —
5
Clock
Frequency,
Max.
Toggle
(
1
twh +
twl
)
250 — 167 — 125 — MHz
tsu1
tco1
th1
tsu2
—
A
—
—
6 GLB Reg. Setup Time before Clock,4 PT Bypass
7 GLB Reg. Clock to Output Delay, ORP Bypass
8 GLB Reg. Hold Time after Clock, 4 PT Bypass
9 GLB Reg. Setup Time before Clock
3.0
—
0.0
3.5
—
3.5
—
—
4.5 — 6.0
W — 4.5 —
E0.0 — 0.0
N5.5 — 7.0
—
6.0
—
—
ns
ns
ns
ns
tco2
— 10 GLB Reg. Clock to Output Delay
— 4.0 — 5.5 — 7.0 ns
R th2
— 11 GLB Reg. Hold Time after Clock
0.0 — 0.0 — 0.0 — ns
O tr1
A 12 Ext. Reset Pin to Output Delay
— 5.5 — 10.0 — 13.5 ns
trw1
F tptoeen
— 13 Ext. Reset Pulse Duration
B 14 Input to Output Enable
3.5 — 5.0 — 6.5 — ns
— 7.0 — 12.0 — 15.0 ns
5 S tptoedis
C 15 Input to Output Disable
— 7.0 — 12.0 — 15.0 ns
A tgoeen
B 16 Global OE Output Enable
— 4.5 — 7.0 — 9.0 ns
4 N tgoedis
C 17 Global OE Output Disable
— 4.5 — 7.0 — 9.0 ns
H IG twh
— 18 External Synchronous Clock Pulse Duration, High 2.0 — 3.0 — 4.0 — ns
twl
— 19 External Synchronous Clock Pulse Duration, Low 2.0 — 3.0 — 4.0 — ns
C S tsu3
— 20 I/O Reg. Setup Time before Ext. Sync Clock (Y1) 3.0 — 3.0 — 3.5 — ns
A E th3
— 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y1)
0.0 — 0.0 — 0.0 — ns
M D 1.
Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
Table 2-0030A/1016EA
v.2.6
2. Refer to Timing Model in this data sheet for further details.
p V 3. Standard 16-bit counter using GRP feedback.
is 5 4. Reference Switching Test Conditions section.
USE
6
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