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IW4053BD 데이터 시트보기 (PDF) - Integral Corp.
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IW4053BD
Analog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS
Integral Corp.
IW4053BD Datasheet PDF : 8 Pages
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CHIP PAD DIAGRAM
IW4053B
Chip marking
1.95 + 0.03
204053
15
14 13 12
11
10
16
09
08
01
03 04
05 06
07
02
(0,0)
Location of marking (mm):
left lower corner x=1.361, y=1.592; right higher corner x=1.423, y=1.652.
Chip thickness
: 0.46
±
0.02mm
PAD LOCATION
Pad No
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
Pin No
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
Location (left lower corner), mm
X
Y
0.116
0.453
0.116
0.175
0.362
0.116
0.669
0.116
1.074
0.116
1.287
0.115
1.699
0.290
1.699
0.620
1.699
0.973
1.700
1.268
1.640
1.583
1.063
1.583
0.756
1.583
0.429
1.583
0.116
1.445
0.116
0.942
Pad size, mm
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
Note: Pad location is given as per passivation layer
INTEGRAL
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