RTL8305S 데이터 시트보기 (PDF) - Realtek Semiconductor
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RTL8305S Datasheet PDF : 24 Pages
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RTL8305S
6.2.2 Buffer Management
The 1M bit embedded memory buffer is divided into a packet buffer, which is used for data buffering, and a page pointer block
(PPB), which is used by the buffer manager. The Packet buffer is constructed of approximately 512 256-byte pages. Each page
includes 8-bytes of header information, which consists of next page pointer, packet byte count, and 248 bytes of data. The
linked pages construct a whole received packet which will be forwarded later according to its destination. The buffer manager
gets free page pointers from PPB and releases to each port to provide space for incoming packet buffering. When the buffer
manager can not support free page pointers any more, it indicates a buffer full condition and 802.3x flow control or back
pressure congestion control is implemented. If no flow control algorithms are activated, packets are dropped.
Buffer Manager
Page177
Page180
Free Page Pointers
Page177 PTR
Page180 PTR
Page193 PTR
Page189 PTR
Page189
Free Page Pointer FIFO
Page193
Frame Buffer
6.2.3 Data Reception
Each port contains a Receive FIFO for incoming packets, which are from physical medium, and a Free Page Pointer FIFO for
packet buffering indexes. Free Page Pointers are obtained from the Buffer Manager. Once a packet is received, it is segmented
into 248-byte pieces (as is fit into pages) and then moved into a packet buffer by the Receive DMA Engine with an 8-byte
header in every page.
6.2.4 Data Forwarding
Each port contains a Transmit FIFO, a Transmit Free Page Pointer FIFO and a Transmit Start Address Queue. The Transmit
Free Page Pointer FIFO stores Free Pages Pointers which have just been released from transmitted packets, and will return
these Free Pages to the Buffer Manager for buffering indexes of the next incoming packets. The Transmit Start Address Queue
keeps the first page pointer of every egress packet, which is from the transmit command issued by the reception port (source
port). The destination ports identify every transmit command on the global bus and receive it if they are the outlets. Finally, the
Transmit DMA engine of each port starts the DMA to move the pages (which construct a whole packet) to Transmit FIFO and
then to the physical medium. For broadcast packets, it’s the duty of the last port which finishes the transmission action last to
return the Transmit Free Page Pointers to the Buffer Manager.
2002/02/19
10
Rev. 1.2
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