SY100S318JC(1999) 데이터 시트보기 (PDF) - Micrel
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SY100S318JC Datasheet PDF : 5 Pages
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5-WIDE 5, 4, 4, 4, 2
OA/OAI GATE
SY100S318
FEATURES
DESCRIPTION
s Max. propagation delay of 800ps
s IEE min. of –55mA
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for
improved noise immunity
s Internal 75KΩ input pull-down resistors
s 70% faster than Fairchild
s 40% lower power than Fairchild
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
The SY100S318 is an ultra-fast 5-wide 5, 4, 4, 4, 2 OR/
AND gate with both true and complementary outputs,
designed for use in high-performance ECL systems. The
inputs on this device have 75KΩ pull-down resistors.
PIN CONFIGURATIONS
D2b
D3b
VEE
VEES
D4b
D1c
D2c
11 10 9 8 7 6 5
12
4
13
3
14
Top View
2
15
PLCC
J28-1
1
16
28
17
27
18
26
19 20 21 22 23 24 25
O
O
VCCA
VCC
VCC
D2e
D1e
D1a
D2a
D3a
24 23 22 21 20 19
D4a
D3c
1
18
D1b
D5a
D4c
2
17
D5a
D1d
3
Top View 16 D4a
D1b
D2b
D2d
4
D3d
5
Flatpack
F24-1
15
D3a
14
D2a
D3b
D4d
6
13
D1a
D4b
7 8 9 10 11 12
D1c
D2c
O
D3c
O
D4c
D1d
D2d
D3d
D4d
PIN NAMES
D1e
Pin
Function
D2e
Dna – Dne
Data Inputs (n = 1...5)
O–O
Data Outputs
VEES
VEE Substrate
VCCA
VCCO for ECL Outputs
Rev.: G
Amendment: /0
1
Issue Date: July, 1999
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