K5L5628JTM 데이터 시트보기 (PDF) - Samsung

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K5L5628JTM

256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

Samsung 

K5L5628JT(B)M

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MCP MEMORY

PIN DESCRIPTION

Ball Name

A0 to A22

A23

DQ0 to DQ15

CEf

CSu

OE

RESET

VPP

WE

WP

CLKf

CLKu

Description

Address Input Balls (Common)

Address Input Balls (Flash Memory)

Data Input/Output Balls (Common)

Chip Enable (Flash Memory)

Chip Select (UtRAM)

Output Enable (Common)

Hardware Reset (Flash Memory)

Accelerates Programming (Flash Memory)

Write Enable (Common)

Write Protection (Flash Memory)

Clock (Flash Memory)

Clock (UtRAM)

Ball Name

RDYf/WAITu

ADVf

ADVu

MRS

LB

UB

Vccf

Vccu

Vccqu

Vss

NC

DNU

Description

Ready Output (Flash Memory)/Wait(UtRAM)

Address Input Valid (Flash Memory)

Address Input Valid (UtRAM)

Mode Register Set (UtRAM)

Lower Byte Enable (UtRAM)

Upper Byte Enable (UtRAM)

Power Supply (Flash Memory)

Power Supply (UtRAM)

Data Out Power (UtRAM)

Ground (Common)

No Connection

Do Not Use

ORDERING INFORMATION

K 5 L 56 28 J T(B) M - D H 18

Samsung MCP Memory

2Chip MCP

Device Type

Demuxed NOR Flash + Demuxed UtRAM

UtRAM Access Time

18.9ns

Flash Access Time

14.5ns(CF 54MHz)

NOR Flash Density

56 : 256Mbit, x16

Package

D : FBGA(Lead Free)

UtRAM Density, (Organization)

28 : 128Mbit, x16, Burst

Operating Voltage

J : 1.8V/1.8V(NOR), 2.6V/1.8V(UtRAM)

Version

1st Generation

Block Architecture

T = Top Boot Block

B = Bottom Boot Block

5

Revision 1.0

November 2004

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