K6R1016V1C 데이터 시트보기 (PDF) - Samsung
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K6R1016V1C Datasheet PDF : 11 Pages
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K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
for AT&T
CMOS SRAM
READ CYCLE*
Parameter
K6R1016V1C-10 K6R1016V1C-12 K6R1016V1C-15 K6R1016V1C-20
Symbol
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
Address Access Time
Chip Select to Output
tRC
10
-
12
-
15
-
20
-
ns
tAA
-
10
-
12
-
15
-
20 ns
tCO
-
10
-
12
-
15
-
20 ns
Output Enable to Valid Output
tOE
-
5
-
6
-
7
-
9
ns
UB, LB Access Time
tBA
-
5
-
6
-
7
-
9
ns
Chip Enable to Low-Z Output
tLZ
3
-
3
-
3
-
3
-
ns
UB, LB Enable to Low-Z Output
tBLZ
0
-
0
-
0
-
0
-
ns
Output Enable to Low-Z Output
tOLZ
0
-
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
tHZ
0
5
0
6
-
7
-
9
ns
Output Disable to High-Z Output
tOHZ
0
5
0
6
-
7
-
9
ns
UB, LB Disable to High-Z Output
tBHZ
0
5
0
6
-
7
-
9
ns
Output Hold from Address Change tOH
3
-
3
-
3
-
3
-
ns
Chip Selection to Power Up Time
tPU
0
-
0
-
0
-
0
-
ns
Chip Selection to Power DownTime tPD
-
10
-
12
-
15
-
20 ns
* The above parameters are also guaranteed at industrial temperature range.
WRITE CYCLE*
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
UB, LB Valid to End of Write
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
tWC
tCW
tAS
tAW
tWP
tWP1
tBW
tWR
tWHZ
tDW
tDH
tOW
K6R1016V1C-10
Min
Max
10
-
7
-
0
-
7
-
7
-
10
-
7
-
0
-
0
5
5
-
0
-
3
-
K6R1016V1C-12
Min
Max
12
-
8
-
0
-
8
-
8
-
12
-
8
-
0
-
0
6
6
-
0
-
3
-
* The above parameters are also guaranteed at industrial temperature range.
K6R1016V1C-15
Min
Max
15
-
9
-
0
-
9
-
9
-
15
-
9
-
0
-
0
7
7
-
0
-
3
-
K6R1016V1C-20
Unit
Min
Max
20
-
ns
10
-
ns
0
-
ns
10
-
ns
10
-
ns
20
-
ns
10
-
ns
0
-
ns
0
9
ns
8
-
ns
0
-
ns
3
-
ns
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL
Address
Data Out
tRC
tAA
tOH
Previous Valid Data
Valid Data
-5-
Revision 3.3
October 2000
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