K6R1016V1D(2001) 데이터 시트보기 (PDF) - Samsung
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K6R1016V1D Datasheet PDF : 11 Pages
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K6R1016V1D
READ CYCLE*
Parameter
Symbol
Read Cycle Time
tRC
Address Access Time
tAA
Chip Select to Output
tCO
Output Enable to Valid Output
tOE
Chip Enable to Low-Z Output
tLZ
Output Enable to Low-Z Output
tOLZ
Chip Disable to High-Z Output
tHZ
Output Disable to High-Z Output
tOHZ
Output Hold from Address Change
tOH
Chip Selection to Power Up Time
tPU
Chip Selection to Power DownTime
tPD
K6R1016V1D-08
Min
Max
8
-
-
8
-
8
-
4
3
-
0
-
0
4
0
4
3
-
0
-
-
8
* The above parameters are also guaranteed at industrial temperature range.
WRITE CYCLE*
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End of Write to Output Low-Z
Symbol
tWC
tCW
tAS
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
tOW
K6R1016V1D-08
Min
Max
8
-
6
-
0
-
6
-
6
-
8
-
0
-
0
4
4
-
0
-
3
-
* The above parameters are also guaranteed at industrial temperature range.
for AT&T
CMOS SRAM
K6R1016V1D-10
Min
Max
10
-
-
10
-
10
-
5
3
-
0
-
0
5
0
5
3
-
0
-
-
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
K6R1016V1D-10
Min
Max
10
-
7
-
0
-
7
-
7
-
10
-
0
-
0
5
5
-
0
-
3
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL)
Address
Data Out
tRC
tAA
tOH
Previous Valid Data
Valid Data
-6-
Revision 1.0
December 2001
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