KB2516 데이터 시트보기 (PDF) - Samsung
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KB2516 Datasheet PDF : 30 Pages
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KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
Symbol
Parameter
Conditions
Sync processor
SOGdet1 SOG sync detect level 1
SOGdet2 SOG sync detect level 2
Analog-to-digital converter
VrefT
Reference top voltage
VrefB
Reference bottom voltage
INL
DC integral non-linearity
Fclk = 75MHz, ramp input
DNL
DC differential non-linearity Fclk = 75MHz, ramp input
SNDR
Signal to noise & distortion
ratio
Fclk = 100MHz
MAXrate Max. conversion rate
CT
Cross talk
Fclk = 100MHz
trD
Digital output rising time
tfD
Digital output falling time
Phase-locked loop
fref
PLL reference clock frequency
fclk
Maximum clock frequency
DRpll
PLL divider ratio
fvco
VCO output clock frequency
tcap
PLL capture time
In start-up condition
trcap
PLL re-capture time
In lock condition
Φstep
Phase shift step
Tamb = 25°C
jPLL
PLL jitter
Fclk = 180MHz
Min. Typ. Max. Unit
0.1
-
-
V
-
-
1.0 V
1.7 1.8
1.2 1.3
-1.0 -
-0.5 -
36
-
1.9 V
1.4 V
1.0 LSB
0.5 LSB
-
dB
170
-
- MHz
-
-
-36 dB
-
-
2
nS
-
-
2
nS
20
-
150 KHz
180
MHz
512
- 4095
17
197 MHz
-
4
-
ms
-
-
300 us
-
7.5
-
deg
-
200
-
ps
4
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