1N4004 데이터 시트보기 (PDF) - STMicroelectronics

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1N4004

OFFLINE FLYBACK CONVERTERS DESIGN METHODOLOGY WITH THE L6590 FAMILY

STMicroelectronics 

Table 7. (continued)

Symbol

Description

IsRMS

Total RMS Secondary Current

IsAC

RMS Secondary Current (AC component only)

AN1262 APPLICATION NOTE

Definition

IsRMS = Ispk ⋅ D-3---'

IsAC = IsR2 MS – IsD2 C

Once this information has been found, it is possible to evaluate the power dissipation of the IC and check for

thermal limitations. Table 8 summarizes the relationships that can be used for this evaluation. In those formulae:

- Tc is the crossover time of the voltage and current waveforms at MOSFET's turn off;

- Cdrain is the total capacitance of the drain, composed of the Coss of the MOSFET, the parasitic capacitance of

the primary winding and, in case, some external capacitance.

As previously said, the worst-case operating conditions for the IC usually occur at Vin = VDCmin, however it is

worthwhile checking the losses also at maximum input voltage, that is at Vin = VPKmax, especially if an external

capacitor is added on the drain.

With the worst-case total losses in the IC it is possible to find the maximum junction-to-ambient thermal resis-

tance allowed for safe operation at maximum ambient temperature.

The operating temperature range of the devices extends to 150 °C, however designing for such high tempera-

ture is not recommended. A reasonable target can be to design for 125 °C maximum die temperature:

Rthmax = -P----Q-----+-----P---1-c---2o---n5---d--–--+--T---P-a---sm---w-b----+----P-----c--a---p-

(3)

Table 8. IC's power losses estimate

Symbol

Description

Pcond

Conduction losses

Psw

Switching losses

Definition

Pcond = IpR2 MS ⋅ RDS(o n)max

Psw ≈ 13-- ⋅ (Vin + VR) ⋅ Ipp k ⋅ Tc ⋅ fsw

PCAP

Capacitive losses

PCA P ≈ 12-- ⋅ Cdrain ⋅ (Vin + VR)2 ⋅ fsw

PQ

Quiescent losses

Assume:

RDS(on) max = 28 Ω (@ Tj = 125 °C)

Tc = 50ns

fsw = 65kHz

Cdrain = 100pF

Iop = 7mA

PQ = VCC · Iop

With the aid of the diagrams shown in fig. 20 it is possible to estimate whether the required thermal resistance

is feasible or not and, in the positive case, how large the on-board copper area is supposed to be. Consider that

copper areas larger than 4 cm2 do not give significant reduction of thermal resistance and may cause PCB lay-

outing to become a serious issue.

If the thermal check does not give positive results, a different heatsinking strategy may be considered, otherwise

a higher maximum duty cycle DX should be used, if possible, to reduce the RMS current. Also a higher Vinmin

9/42

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