KM718V887 데이터 시트보기 (PDF) - Samsung
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KM718V887 Datasheet PDF : 16 Pages
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KM718V887
Output Load(A)
Dout
Z0=50Ω
256Kx18 Synchronous SRAM
RL=50Ω
30pF*
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
Output Load(B)
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
319Ω / 1667Ω
353Ω / 1538Ω
5pF*
* Capacitive Load consists of all components of
the test environment.
Fig. 1
* Including Scope and Jig Capacitance
AC TIMING CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
PARAMETER
SYMBOL
KM718V887-7
MIN MAX
KM718V887-8
MIN MAX
Cycle Time
tCYC
8.5
-
10
-
Clock Access Time
tCD
-
7.5
-
8
Output Enable to Data Valid
tOE
-
3.5
-
3.5
Clock High to Output Low-Z
tLZC
0
-
0
-
Output Hold from Clock High
tOH
2
-
2
-
Output Enable Low to Output Low-Z
tLZOE
0
-
0
-
Output Enable High to Output High-Z
tHZOE
-
3.5
-
3.5
Clock High to Output High-Z
tHZC
2
3.5
2
3.5
Clock High Pulse Width
tCH
3
-
4
-
Clock Low Pulse Width
tCL
3
-
4
-
Address Setup to Clock High
tAS
2.0
-
2.0
-
Address Status Setup to Clock High
tSS
2.0
-
2.0
-
Data Setup to Clock High
tDS
2.0
-
2.0
-
Write Setup to Clock High(GW, BW, WEx)
tWS
2.0
-
2.0
-
Address Advance Setup to Clock High
tADVS
2.0
-
2.0
-
Chip Select Setup to Clock High
tCSS
2.0
-
2.0
-
Address Hold from Clock High
tAH
0.5
-
0.5
-
Address Status Hold from Clock High
tSH
0.5
-
0.5
-
Data Hold from Clock High
tDH
0.5
-
0.5
-
Write Hold from Clock High(GW, BW, WEx)
tWH
0.5
-
0.5
-
Address Advance Hold from Clock High
tADVH
0.5
-
0.5
-
Chip Select Hold from Clock High
tCSH
0.5
-
0.5
-
ZZ High to Power Down
tPDS
2
-
2
-
ZZ Low to Power Up
tPUS
2
-
2
-
KM718V887-9
MIN MAX
12
-
-
9
-
3.5
0
-
2
-
0
-
-
3.5
2
3.5
4.5
-
4.5
-
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
2
-
2
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycle
cycle
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
4. At any given voltage and temperature, tHZC is less than tLZC.
-8-
December 1998
Rev. 2.0
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