74LV4040 데이터 시트보기 (PDF) - Philips Electronics
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74LV4040 Datasheet PDF : 14 Pages
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Philips Semiconductors
12-stage binary ripple counter
Product specification
74LV4040
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V v 3.6V
VM = 0.5V * VCC at VCC t 2.7V and w 4.5V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI
CP INPUT VM
GND
VOH
Qn OUTPUT
VOL
tPHL
1/fmax
tW
VM
tPLH
SV00322
Figure 7. Clock (CP) to output (Qn) propagation delays, the
clock pulse width and the maximum clock pulse frequency
VI
MR INPUT
GND
VI
CP INPUT
GND
VOH
Qn OUTPUT
GND
tW
trem
tPHL
SV00908
Figure 8. Master reset (MR) pulse width, the master reset to
output (Qn) propagation delays and the master reset to clock
(CP) removal time
TEST CIRCUIT
VCC
PULSE
GENERATOR
VI
RT
D.U.T.
VO
50pF
CL
RL = 1k
Test Circuit for switching times
DEFINITIONS
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
RT = Termination resistance should be equal to ZOUT of pulse generators.
TEST
tPLH/tPHL
VCC
< 2.7V
2.7–3.6V
VI
VCC
2.7V
SV00901
Figure 9.Load circuitry for switching times
1998 Jun 23
8
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