74F256 데이터 시트보기 (PDF) - Philips Electronics
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74F256 Datasheet PDF : 12 Pages
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Philips Semiconductors
Dual addressable latch
Product specification
74F256
LOGIC SYMBOL
3
13
IEC/IEEE SYMBOL
3
Z5
13
Z6
15
G4
Da
Db
14
E
1
A0
2
A1
15
MR
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b
4 56 7
9 10 11 12
VCC = Pin 16
GND = Pin 8
SF00806
5, 7D
4
1
C7
1
0
0
2
G
0
3
1
1
2
4R
5
6
3
7
14
6, 8D
1
C8
9
0
4R
1
10
2
11
3
12
SF00807
FUNCTION TABLE
INPUTS
OUTPUTS
MR
E
D
A0
A1
Q0
Q1
Q2
Q3
OPERATING MODE
L
H
X
X
X
L
L
L
L
Master Reset
L
L
d
L
L
Q=d
L
L
L Demultiplex (active-High decoder when D=H)
L
L
d
H
L
L
Q=d
L
L
L
L
d
L
H
L
L
Q=d
L
L
L
d
H
H
L
L
L
Q=d
H
H
X
X
X
q0
q1
q2
q3 Store (do nothing)
H
L
d
L
L
Q=d
q1
q2
q3
H
L
d
H
L
q0
Q=d
q2
q3
Addressable Latch
H
L
d
L
H
q0
q1
Q=d
q3
H
L
d
H
H
q0
q1
q2
Q=d
H = High voltage level
L = Low voltage level
X = Don’t care
d = High or Low data one setup time prior to the Low-to-High Enable transition
q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared.
1988 Nov 29
3
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