KSZ8041NLJ 데이터 시트보기 (PDF) - Micrel

부품명

상세내역

제조사

KSZ8041NLJ

10/100 Ethernet Transceiver with Extended Temperature Support

Micrel 

Micrel, Inc.

KSZ8041NLJ

Strapping Options

Pin Number Pin Name

Type(1) Pin Function

15

PHYAD2

Ipd/O

The PHY Address is latched at power-up / reset and is configurable to any value from

14

PHYAD1

Ipd/O

1 to 7.

13

PHYAD0

Ipu/O

The default PHY Address is 00001.

PHY Address bits [4:3] are always set to ‘00’.

18

CONFIG2

Ipd/O

The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as

29

CONFIG1

Ipd/O

follows:

28

CONFIG0

Ipd/O

CONFIG[2:0] Mode

000

MII (default)

001

RMII

010

Reserved – not used

011

Reserved – not used

100

MII 100Mbps Preamble Restore

101

Reserved – not used

110

Reserved – not used

111

Reserved – not used

20

ISO

Ipd/O ISOLATE mode

Pull-up = Enable

Pull-down (default) = Disable

During power-up / reset, this pin value is latched into register 0h bit 10.

31

SPEED

Ipu/O

SPEED mode

Pull-up (default) = 100Mbps

Pull-down = 10Mbps

During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed

Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the

Speed capability support.

16

DUPLEX

Ipu/O

DUPLEX mode

Pull-up (default) = Half Duplex

Pull-down = Full Duplex

During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex

Mode.

30

NWAYEN

Ipu/O

Nway Auto-Negotiation Enable

Pull-up (default) = Enable Auto-Negotiation

Pull-down = Disable Auto-Negotiation

During power-up / reset, this pin value is latched into register 0h bit 12.

Note:

1. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.

Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during

power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII signals to be latched high. In this case,

it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE

mode, or is not configured with an incorrect PHY Address.

April 2010

10

M9999-040110-1.0

Share Link: