SAA7346H 데이터 시트보기 (PDF) - Philips Electronics

부품명

상세내역

제조사

SAA7346H

Shock absorbing RAM addresser

Philips Electronics 

Philips Semiconductors

Shock absorbing RAM addresser

Preliminary specification

SAA7346

handbook, full pagewidth

flush + reset +

(empty and echo)

RESET

0

flush + reset

flush + reset

reset and sow

HOLD first nibble FILL

full

6

1

FILL

2

SSD and

(NSF + S_NSF)

HOLD

5

SSD

PFB

PFB

SSD

SHOCK

7

SSD

SSD

HOLD

4

first nibble

NSF +

S_NSF

FILL

3

MGB432

Fig.5 State machine flow diagram.

During normal operation the FIFO will fill up because

writing is carried out twice as fast as reading; this is the fill

mode. If the FIFO is full the monitor will detect and set the

full flag. At the same time the fill flag will be reset thus

preventing audio data from being written in to the FIFO.

When the microcontroller reads the full flag from the status

register, the servo control should jump back one track. The

microcontroller enters a wait loop until the same absolute

time subcode frame turns by again; this is the hold mode.

When the spot is found again the microcontroller should

set the PFB flag in the command register and the

SAA7346 will resume writing to the DRAM. While in fill

mode the write pointer address is saved at the end of each

subcode frame. When the player exists hold mode it

restores the saved address and continues writing after the

last sample.

When a shock is detected the SAA7346 will enter shock

mode. The shock mode will last until the PFB is set by the

microcontroller or the FIFO is flushed, reset or runs empty.

Microcontroller interface

The SAA7346 has a 3-line microcontroller interface which

is compatible with TDA1301, TDA1303 and SAA7345.

WRITING DATA TO THE SAA7346

The SAA7346 command register is shown in Table 1. This

can be written to via the microcontroller interface as shown

in Fig.6. The command register flags functions are shown

in Table 2.

Table 1 SAA7346 microcontroller interface registers.

REGISTER

Command

Status

BIT 7

flush

Lm

BIT 6

bypass

Lm1

BIT 5

echo

FRM_ER

BIT 4

jmp_bz

NSF

BIT 3

otd_p

full

BIT 2

e_rot_sd

empty

BIT 1

µCsd

SSD

BIT 0

PFB

fill

July 1994

7

Share Link: