LB11872H(2002) 데이터 시트보기 (PDF) - SANYO -> Panasonic
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LB11872H Datasheet PDF : 13 Pages
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LB11872H
Overview of the LB11872H
1. Speed Control Circuit
This IC adopts a PLL speed control technique and provides stable motor operation with high precision and low jitter.
This PLL circuit compares the phase error at the edges of the CLK signal (falling edges) and FG signal (rising edges
(low to high transitions) on the IN1 input), and the IC uses the detected error to control the motor speed.
During this control operation, the FG servo frequency will be the same as the CLK frequency.
fFG (servo) = fCLK
2. Output Drive Circuit
To minimize motor noise, this IC adopts three-phase full-wave current linear drive. This IC also adopts a midpoint
control technique to prevent ASO destruction of the output transistors.
Reverse torque braking is used during motor deceleration during speed switching and lock pull-in. In stop mode, the
drive is cut and the motor is left in the free-running state.
Since the output block may oscillate depending on the motor actually used, capacitors (about 0.1 µF) must be inserted
between the OUT pins and ground.
3. Hall Input Signals
This IC includes an AGC circuit that minimizes the influence on the output of changes in the Hall signal input
amplitudes due to the motor used. However, note that if there are discrepancies in the input amplitudes between the
individual phases, discrepancies in the output phase switching timing may occur.
An amplitude (differential) of at least 50 mVp-p is required in the Hall input signals. However, if the input amplitude
exceeds 350 mVp-p, the AGC circuit control range will be exceeded and kickback may occur in the output.
If Hall signal input frequencies in excess of 1 kHz (the frequency in a single Hall input phase) are used, internal IC
heating during startup and certain other times (that is, when the output transistors are saturated) may increase.
Reducing the number of magnetic poles can be effective in dealing with problem.
The IN1 Hall signal is used as the FG signal for speed control internally to the IC. Since noise can easily become a
problem, a capacitor must be inserted across this input. However, since this could result in differences between the
signal amplitudes of the three phases, capacitors must be inserted across all of the three input phases.
Although VCC can be used as the Hall element bias power supply, using VREG can reduce the chances of problems
occurring during noise testing and at other times. If VREG is used, since there is no longer any need to be concerned
with the upper limit of the Hall amplifier common-mode input voltage range, bias setting resistors may be used only
on the low side.
4. Power Saving Circuit
This IC goes into a power saving state that reduces the current drain in the stop state. The power saving state is
implemented by removing the bias current from most of the circuits in the IC. However, the 6.3 V regulator output is
provided in the power saving state.
5. Reference Clock
Care must be taken to assure that no chattering or other noise is present on the externally input clock signal. Although
the input circuit does have hysteresis, if problems do occur, the noise must be excluded with a capacitor.
This IC includes an internal clock cutoff protection circuit. If a signal with a frequency below that given by the
formula below is input, the IC will not perform normal control, but rather will operate in intermittent drive mode.
f (Hz) .=. 0.64 ÷ CCSD CCSD (µF): The capacitor inserted between the CSD pin and ground.
When a capacitor of 0.022 µF is used, the frequency will be about 29 Hz.
If the IC is set to the start state when the reference clock signal is completely absent, the motor will turn somewhat
and then motor drive will be shut off. After the motor stops and the rotor constraint protection time elapses, drive will
not be restarted, even if the clock signal is then reapplied. However, drive will restart if the clock signal is reapplied
before the rotor constraint protection time elapses.
No. 7257 -10/13
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