LC3564CM 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LC3564CM

64K (8192-word × 8-bit) SRAM with OE, CE1, and CE2 Control Pins

SANYO -> Panasonic 

LC3564CM, CT-55U/70U

Data Retention Characteristics at Ta = –40 to +85°C

Parameter

Data retention supply voltage

Data retention supply current

Chip enable setup time

Chip enable hold time

Note *: tRC is the read cycle time.

Symbol

Conditions

VDR

ICCDR

tCDR

tR

VCE2 ≤ 0.2 V or

VCE1 ≥ VCC – 0.2 V, VCE2 ≥ VCC – 0.2 V

VCC = 3V, VCE2 ≤ 0.2 V,

or VCE1 ≥ VCC – 0.2 V,

VCE2 ≥ VCC – 0.2 V

Ta ≤ 70°C

Ta ≤ 85°C

min

2.0

0

tRC*

Ratings

typ

Unit

max

5.5

µA

0.8

µA

2.5

ns

ns

Data Retention Waveforms (1): CE1 Control

tCDR

Data retention mode

tR

VCC

VCCL *

VIH

VDR

VCE1

GND

VCE1 ≥ VCC–0.2V

A13517

Data Retention Waveforms (2): CE2 Control

VCC

VCCL *

VCE2

VDR

VIL

GND

Data retention mode

tCDR

tR

VCE2 ≤ 0.2V

A13518

Note *:In 5-V operation: 4.5 V

In 3-V operation: 2.7 V

Notes on Circuit Design

When actually design a circuit using these devices, take the following points into consideration and design the circuit so

that none of the maximum rating items are ever exceeded.

• Variations in the supply voltage

• Variations in the electrical characteristics of components such as semiconductor devices, resistors, and capacitors.

• Ambient temperature

• Variations in input and clock signals

• Possible application of abnormal pulses

Also, these devices must be operated within the ranges stipulated in the allowable operating ranges.

If CMOS IC input pins are left open, intermediate potential input voltages may occur leading to incorrect operation due

to through currents or other phenomenon. Applications must handle unused input pins appropriately.

No. 6635-10/11

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