LC3564CM 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LC3564CM

64K (8192-word × 8-bit) SRAM with OE, CE1, and CE2 Control Pins

SANYO -> Panasonic 

Block Diagram

LC3564CM, CT-55U/70U

A0 to A12

Memory cell array

VCC

GND

I/O1 to I/O8

Output

buffer

Data control

circuit

Input

data

buffer

CE1

CE2

Control

circuit

WE

OE

Pin Functions

A0 to A12

WE

OE

CE1, CE2

I/O1 to I/O8

VCC, GND

Address inputs

Read/write control input

Output enable input

Chip enable inputs

Data I/O

Power supply and ground

Function Table

Mode

CE1 CE2 OE WE

I/O

Supply current

Read cycle

L

H

L

H

Data output

Write cycle

L

H

X

L

Data input

Output disable

L

H

H

H High impedance

H

X

X

X High impedance

Not selected

X

L

X

X High impedance

ICCA

ICCA

ICCA

ICCS

ICCS

X : H or L

A13512

No. 6635-3/11

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