LC7153M 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LC7153M

Universal Dual-PLL Frequency Synthesizers

SANYO -> Panasonic 

LC7153, 7153M

Figure 1. Dual charge-pump circuit

The phase-detector secondary output is high impedance increasing the LPF time constant and improving sideband

when the PLL is locked. In this case, R1 becomes R1M, and modulation response.

Test Mode

TEST should be LOW or open for normal operation.

Serial Input Data

Serial data should be input only after fXIN has become

stable.

Mode 1 command format and functions

The Mode 1 command comprises the data bits which de-

termine the PLLA and PLLB programmable divider ratios.

The command format is shown in figure 2. Bits DA0 to

DA15 and DB0 to DB15 determine the PLLA and PLLB

programmable divider ratios, respectively. Bit DA0 is the

first bit received. The range of allowable divider ratios is N

=256 (0100H) to 65535 (FFFFH).

Figure 2. Mode 1 command (programmable divider data)

No.4160–6/11

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