LC7153M 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LC7153M

Universal Dual-PLL Frequency Synthesizers

SANYO -> Panasonic 

LC7153, 7153M

Table 4. Unlock detector thresholds

UL0

UL1

LDA, LDB phase

error threshold

fXIN=4MHz

Example phase error thresholds (µs)

fXIN=7.2MHz

fXIN=8MHz fXIN=10.24MHz fXIN=12.8MHz

0

0

0

0

0

0

0

0

1

0

0

1

1

1

±4/fXIN

±16/fXIN

±64/fXIN

±1.00

±4.00

±16.00

±0.55

±2.22

±8.88

±0.50

±2.00

±8.00

±0.39

±1.56

±6.25

±0.31

±1.20

±5.00

Bits UE0 and UE1 determine the unlock extension, or de-

lay, before the unlock detector outputs, LDA and LDB, can

change state. The extension for different reference frequen-

cies is shown in table 5. However, if a phase-error thresh-

old of zero is set using UL0 and UL1, no output extension

occurs.

Table 5. LDA, LDB output extension

UE0

UE1

LDA, LDB output

extension

0

0

4/fref

1

0

8/fref

0

1

32/fref

1

1

64/fref

Bit DZ is the dead-zone selection bit. It selects the phase-

insensitive bandwidth, or dead zone, of the phase compara-

tor. When DZ=1, DZB mode is selected, and when DZ=0,

DZA mode. DZB mode has larger dead zone than DZA

mode.

Example output extensions (ms)

fref=1kHz

4.0 (typ)

fref=5kHz

0.8

fref=12.5kHz

0.32

8.0

1.6

0.64

32.0

6.4 (typ)

2.56

64.0

12.8

5.12 (typ)

Bits T0, T1 and T2 are test bits. They should be set to 0 for

normal operation.

No.4160–8/11

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