LC72725KM, 72725KV
Input/Output Data Format
TEST
MODE
Circuit Operation Mode
0
0
Master read out mode
0
1
Slave read out mode
1
0
Standby mode (crystal oscillator stopped)
1
1
IC test mode which is not available to user applications.
RDCL Pin
Clock output
Clock input
-
-
RDS-ID/READY Pin
RDS-ID output
READY output
-
-
RST = 0
RST = 1
RST Pin
Normal operation
RDS-ID • demodulation circuit clear + READY • memory clear (when slave mode)
RDS-ID/READY Pin
Master mode
RDS-ID output (Active-high)
Slave mode
READY output (Active-high)
Note: RDS-ID(READY) pin is an n-channel open-drain output, and requires an external pull-up resistor to output data.
RDCL/RDDA Output Timing in Master Mode
RDCL output
421µs 421µs
Tp1
RDDA output
17µs Tp21
17µs
RDS-ID Output Timing
RDS-ID High/Low High/Low High/Low High/Low High/Low High/Low High/Low
RDCL
RDDA
Note: RDS-ID is High: data with high RDS reliability, Low: data with low RDS reliability
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