LC75816E 데이터 시트보기 (PDF) - SANYO -> Panasonic
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LC75816E
SANYO -> Panasonic
LC75816E Datasheet PDF : 43 Pages
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LC75816E, 75816W
Pin Functions
Pin
S1 to S63
S64/COM10
S65/COM9
COM1 to COM8
KS1/P1
KS2/P2
KS3 to KS6
KI1 to KI5
Pin No.
LC75816E
3 to 65
66
67
LC75816W
1 to 63
64
65
Function
Segment driver outputs.
The S64/COM10, S65/COM9 pins can be used as common
driver output under the “set display technique” instruction.
75 to 68
76
77
78 to 81
73 to 66
74
75
76 to 79
Common driver outputs.
Key scan outputs. Although normal key scan timing lines require
diodes to be inserted in the timing lines to prevent shorts, since
these outputs are unbalanced CMOS transistor outputs, these
outputs will not be damaged by shorting when these outputs are
used to form a key matrix. The KS1/P1 and KS2/P2 pins can be
used as general-purpose output ports under the "set key scan
output port/general-purpose output port state" instruction.
82 to 86
80 to 84
Key scan inputs.
These pins have built-in pull-down resistors.
OSCI
OSCO
CE
CL
DI
DO
INH
97
95
Oscillator connections. An oscillator circuit is formed by
96
94
connecting an external resistor and capacitor at these pins.
100
98
Serial data interface connections to the controller. Note that DO,
being an open-drain output, requires a pull-up resistor.
1
99
CE : Chip enable
2
100
CL : Synchronization clock
DI : Transfer data
99
97
DO : Output data
Input that turns the display off, disables key scanning, and
forces the general-purpose output ports low.
• When INH is low (VSS):
• Display off
98
96
S1 to S63 = “L” (VLCD4).
S64/COM10, S65/COM9 = “L” (VLCD4).
COM1 to COM8 = “L” (VLCD4).
• General-purpose output ports P1, P2 = low (VSS)
• Key scanning disabled: KS1 to KS6 = low (VSS)
• All the key data is reset to low.
• When INH is high (VDD):
• Display on
• The state of the pins as key scan output pins or
general-purpose output ports can be set with the
"set key scan output port/general-purpose output
port state" instruction.
• Key scanning is enabled.
However, serial data can be transferred when the INH pin is low.
Active
—
—
—
H
—
—
H
—
—
L
TEST
95
93
This pin must be connected to ground.
—
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VDD
VLCD
VSS
LCD drive 4/4 bias voltage (high level) supply pin. The level on
this pin can be changed by the display contrast adjustment circuit.
89
87
However, (VLCD0 – VLCD4) must be greater than or equal to 4.5
—
V. Also, external power must not be applied to this pin since the
pin circuit includes the display contrast adjustment circuit.
LCD drive 3/4 bias voltage (middle level) supply pin. This pin can
90
88
be used to supply the 3/4 (VLCD0 – VLCD4) voltage level externally.
—
LCD drive 2/4 bias voltage (middle level) supply pin. This pin can
91
89
be used to supply the 2/4 (VLCD0 - VLCD4) voltage level externally.
—
LCD drive 1/4 bias voltage (middle level) supply pin. This pin can
92
90
be used to supply the 1/4 (VLCD0 – VLCD4) voltage level externally.
—
LCD drive 0/4 bias voltage (low level) supply pin. Fine
adjustment of the display contrast can be implemented by
93
91
connecting an external variable resistor to this pin.
—
However, (VLCD0 – VLCD4) must be greater than or equal to 4.5
V, and VLCD4 must be in the range 0 V to 1.5 V, inclusive.
87
85
Logic block power supply connection. Provide a voltage of
between 4.5 and 6.0 V.
—
LCD driver block power supply connection. Provide a voltage of
88
86
between 7.0 and 10.0 V when the display contrast adjustment
circuit is used and provide a voltage of between 4.5 and 10.0 V
—
when the circuit is not used.
94
92
Power supply connection. Connect to ground.
—
I/O Handling when unused
O
OPEN
O
OPEN
O
OPEN
I
GND
I
GND
O
OPEN
I
I
GND
I
O
OPEN
I
VDD
I
—
O
OPEN
I
OPEN
I
OPEN
I
OPEN
I
GND
—
—
—
—
—
—
No. 7142-7/43
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