LC7940KD 데이터 시트보기 (PDF) - SANYO -> Panasonic
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LC7940KD Datasheet PDF : 13 Pages
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LC7940KD / LC7941KDR
100×240-Pixel LCD Panel Application
A100×240-Pixel LCD Panel requires the following drivers.
• 3×LC7940KD (or LC7941KDR) drivers
• 2×LC7942KD drivers
An example using 1/100 duty cycle is shown below.
Frame signal
1,79
(m, n): Pixel address
Segment line (n)
Common line (m)
DIO1 O1
RS/LS O2
LC7942KD
#1
CP
M O63
DIO64 O64
DIO1 O1
RS/LS O2
LC7942KD
#2
CP
M O36
DIO64
O37 to 64
are open.
1,1
1,2
∼ ∼ ∼ 1,79 1,80 1,81 1,82
1,160 1,161
1,240
2,1 2,2
2,240
LCD Panel (100×240 Pixels)
∼ 63,1 63,2
64,1 64,2
∼ 65,1 65,2
66,1 66,2
64,80 64,81
65,80 65,81
∼
∼
64,160 64,161
64,240
∼ ∼ 65,160 65,161
65,240
∼ ∼ ∼ 100,1 100,2
100,79 100,80 100,81 100,82
100,160 100,161
100,240
O1
CDI
O2
O79
LC7940KD
(LC7941KDR) #1
O80
CDO
O1 O2
O80
LC7940KD
CDI (LC7941KDR) #2 CDO
O1 LC7940KD O80
(LC7941KDR)
CDI #3 CDO
(1) The LC7942KD chips are cascaded by connecting DIO64 on chip 1 to DIO1 on chip 2.
For a 100-bit shift register, O37 to O64 on chip 2 are left open.
(2) The LC7940KD (or LC7941KDR) chips are cascaded by connecting CDO on chip 1 to CDI on chip 2,
and CDO on chip 2 to CDI on chip 3. CDI on chip 1 is tied to GND, and CDO on chop 3 is not used.
This configulation allows the input of 240-bit serial data.
No.A0573-10/13
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