3293-14 데이터 시트보기 (PDF) - Peregrine Semiconductor

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3293-14

1.8 GHz / 550 MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis

Peregrine Semiconductor 

PE3293

Product Specification

Table 11. foLD Programming Truth Table

X = don’t care condition

foLD

Output State

Disabled (Note 1)

PLL 1 Lock detect

(Note 2) (LD1)

PLL2 Lock detect

(Note 2) (LD2)

PLL1 / PLL2 Lock detect

(Note 2)

PLL1 Reference divider output (fc1)

PLL2 Reference divider output (fc2)

PLL1 Programmable divider output (fp1)

PLL2 Programmable divider output (fp2)

Serial data out

Reserved

Reserved

Counter reset (Note 3)

C14

(PLL1F0)

0

0

0

0

1

0

1

0

1

1

1

1

C13

(PLL1LD)

0

1

0

1

X

X

X

X

0

0

1

1

C24

(PLL2F0)

0

0

0

0

0

1

0

1

1

1

1

1

C23

(PLL2LD)

0

0

1

1

0

0

1

1

0

1

0

1

Note 1: When the foLD is disabled the output is a CMOS LOW.

Note 2: Lock detect indicates when the VCO frequency is in “lock”. When PLL1 is in lock and PLL1 lock detect is selected, the foLD pin will be HIGH with

narrow pulses LOW. When PLL2 is in lock and PLL2 lock detect is selected, the foLD pin will be HIGH with narrow pulses LOW. When PLL1 / PLL2 lock

detect is selected the foLD pin will be HIGH with narrow pulses LOW only when both PLL1 and PLL2 are in lock.

Note 3: The counter reset state when activated resets all counters. Upon removal of the reset, counters M, A, and F resume counting in

close alignment with the R counter (the maximum error is one prescaler cycle). The reset bits can be activated to allow smooth

acquisition upon powering up.

Programming the Pre-scaler

P2 and P1 are used for internal testing of the prescaler and must be programmed with 0,0 for normal

PLL operation.

PEREGRINE SEMICONDUCTOR CORP.  | http://www.peregrine-semi.com

Copyright  Peregrine Semiconductor Corp. 2003

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