LH28F800SG-L 데이터 시트보기 (PDF) - Sharp Electronics
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LH28F800SG-L Datasheet PDF : 45 Pages
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The selected block can be locked or unlocked
individually by the combination of sixteen block lock
bits and the RP# or WP#. Block erase or word
write must not be carried out by setting block lock
bits and setting WP# to low and RP# to VIH. Even
if WP# is high state or RP# is set to VHH, block
erase and word write to locked blocks is prohibited
by setting permanent lock bit.
The status register or RY/BY# indicates when the
WSM’s block erase, word write, or lock-bit
configuration operation is finished.
The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase, word write, or
lock-bit configuration. RY/BY#-high indicates that
the WSM is ready for a new command, block erase
is suspended (and word write is inactive), word
write is suspended, or the device is in deep power-
down mode.
The access time is 70 ns (tAVQV) at the VCC supply
voltage range of 4.75 to 5.25 V over the
temperature range, 0 to +70°C (LH28F800SG-L)/
– 40 to +85°C (LH28F800SGH-L). At 4.5 to 5.5 V
VCC, the access time is 80 ns or 100 ns. At lower
VCC voltage, the access time is 85 ns or 100 ns
(3.0 to 3.6 V) and 100 ns or 120 ns (2.7 to 3.0 V).
The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 1 mA at
5 V VCC and 3 mA at 2.7 to 3.6 V VCC.
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
When CE# and RP# pins are at VCC, the ICC
CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (tPHQV) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
32 k-Word Block 15
32 k-Word Block 14
32 k-Word Block 13
32 k-Word Block 12
32 k-Word Block 11
32 k-Word Block 10
32 k-Word Block
9
32 k-Word Block
8
32 k-Word Block
7
32 k-Word Block
6
32 k-Word Block
5
32 k-Word Block
4
32 k-Word Block
3
32 k-Word Block
2
32 k-Word Block
1
32 k-Word Block
0
Fig. 1 Memory Map
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