LH5164AVH 데이터 시트보기 (PDF) - Sharp Electronics

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LH5164AVH

CMOS 64K (8K × 8) Static RAM

Sharp Electronics 

CMOS 64K (8K × 8) Static RAM

tWC

A0 - A12

OE

tAW

tCW

(NOTE 1)

tWR

(NOTE 2)

CE1

tCW

tWR

CE2

tAS

(NOTE 3)

tWP

tWR

(NOTE 4)

WE

tOHZ

DOUT

tDW

tDH

(NOTE 5)

DIN

DATA VALID

NOTES:

1. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2

HIGH transition, to the time when the writing is finished.

2. tWR is defined as the time from writing finish to address change.

3. tAS is defined as the time from address change to writing start.

4. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP).

5. When I/O pins are in the output state, input signals with the opposite logic level must not be applied.

Figure 6. Write Cycle (OE Controlled)

LH5164AVH

5164AVH-5

7

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