LH532100BSR 데이터 시트보기 (PDF) - Sharp Electronics

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LH532100BSR

CMOS 2M (256K × 8) MROM

Sharp Electronics 

LH532100B

FEATURES

• 262,144 words × 8 bit organization

• Access time: 150 ns (MAX.)

• Low-power consumption:

Operating: 275 mW (MAX.)

Standby: 550 µW (MAX.)

• Static operation

• Mask-programmable OE/OE and

OE1/OE1/DC

• TTL compatible I/O

• Three-state outputs

• Single +5 V power supply

• Packages:

32-pin, 600-mil DIP

32-pin, 525-mil SOP

32-pin, 450-mil QFJ (PLCC)

32-pin, 8 × 20 mm2 TSOP (Type I)

32-pin, 400-mil TSOP (Type II)

• JEDEC standard EPROM pinout (DIP)

CMOS 2M (256K × 8) MROM

DESCRIPTION

The LH532100B is a 2M-bit mask-programmable

ROM organized as 262,144 × 8 bits. It is fabricated

using silicon-gate CMOS process technology.

PIN CONNECTIONS

32-PIN DIP

32-PIN SOP

TOP VIEW

OE1/OE1/DC 1

A16 2

A15 3

A12 4

A7 5

A6 6

A5 7

A4 8

A3 9

A2 10

A1 11

A0 12

D0 13

D1 14

D2 15

GND 16

32 VCC

31 DC

30 A17

29 A14

28 A13

27 A8

26 A9

25 A11

24 OE/OE

23 A10

22 CE

21 D7

20 D6

19 D5

18 D4

17 D3

532100B-1

Figure 1. Pin Connections for DIP and

SOP Packages

32-PIN QFJ

TOP VIEW

D7

CE

A10

OE/OE

A11

A9

A8

A13

A14

20 19 18 17 16 15 14

21

13 D0

22

12 A0

23

11 A1

24

10 A2

25

9 A3

26

8 A4

27

7 A5

28

6 A6

29

5 A7

30 31 32 1 2 3 4

532100B-7

Figure 2. Pin Connections QFJ

(PLCC) Package

1

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