LH532600D 데이터 시트보기 (PDF) - Sharp Electronics

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LH532600D

CMOS 2M (256K × 8/128K × 16) MROM

Sharp Electronics 

LH532600

CMOS 2M (256K × 8/128K × 16) MROM

FEATURES

• 262,144 words × 8 bit organization

(Byte mode)

131,072 words × 16 bit organization

(Word mode)

• Access time: 100 ns (MAX.)

• Static operation

• TTL compatible I/O

• Three-state outputs

• Single +5 V power supply

• Power consumption:

Operating: 412.5 mW (MAX.)

Standby: 550 µW (MAX.)

• Mask-programmable control pin:

Pin 1 = OE1/OE1/DC

• Packages:

40-pin, 600-mil DIP

40-pin, 525-mil SOP

48-pin, 10 × 20 mm2 TSOP (Type I)

DESCRIPTION

The LH532600 is a 2M-bit mask-programmable ROM

organized as 262,144 × 8 bits (Byte mode) or 131,072

× 16 bits (Word mode) that can be selected by BYTE

input pin. It is fabricated using silicon-gate CMOS proc-

ess technology.

PIN CONNECTIONS

40-PIN DIP

40-PIN SOP

TOP VIEW

OE1/OE1/DC 1

A7 2

A6 3

A5 4

A4 5

A3 6

A2 7

A1 8

A0 9

CE 10

GND 11

OE 12

D0 13

D8 14

D1 15

D9 16

D2 17

D10 18

D3 19

D11 20

40 A8

39 A9

38 A10

37 A11

36 A12

35 A13

34 A14

33 A15

32 A16

31 BYTE

30 GND

29 D15/A-1 (LSB)

28 D7

27 D14

26 D6

25 D13

24 D5

23 D12

22 D4

21 VCC

532600-1

Figure 1. Pin Connections for DIP and

SOP Packages

1

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