LH7A400 데이터 시트보기 (PDF) - NXP Semiconductors.

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LH7A400

32-Bit System-on-Chip

NXP Semiconductors. 

LH7A400

NXP Semiconductors

32-Bit System-on-Chip

Table 3. Functional Pin List (Cont’d)

BGA

PIN

L6

M6

N6

M7

M8

N4

P4

R4

T4

N7

P8

P5

R5

T5

R6

R8

LFBGA

PIN

SIGNAL

DESCRIPTION

RESET

STATE

P4

PG2/

nPCIOR

• GPIO Port G

• I/O Read Strobe for PC Card (PCMCIA or CF) in LOW: PG2

single or dual card mode

R3

PG3/

nPCIOW

• GPIO Port G

• I/O Write Strobe for PC Card (PCMCIA or CF) in LOW: PG3

single or dual card mode

• GPIO Port G

T2 PG4/nPCREG • Register Memory Access for PC Card (PCMCIA LOW: PG4

or CF) in single or dual card mode

• GPIO Port G

• Card Enable 1 for PC Card (PCMCIA or CF) in

P5 PG5/nPCCE1 single or dual card mode. This signal and

LOW: PG5

nPCCE2 are used by the PC Card for decoding

low and high byte accesses.

• GPIO Port G

• Card Enable 2 for PC Card (PCMCIA or CF) in

R4 PG6/nPCCE2 single or dual card mode. This signal and

LOW: PG6

nPCCE1 are used by the PC Card for decoding

low and high byte accesses.

• GPIO Port G

T3 PG7/PCDIR • Direction for PC Card (PCMCIA or CF) in single LOW: PG7

or dual card mode

P6

PH0/

PCRESET1

• GPIO Port H

• Reset Card 1 for PC Card (PCMCIA or CF) in sin- Input: PH0

gle or dual card mode

• GPIO Port H

T4

PH1/CFA8/

PCRESET2

• Address Bit 8 for PC Card (CF) in single card mode

• Reset Card 2 for PC Card (PCMCIA or CF) in

Input: PH1

dual card mode

• GPIO Port H

M7

PH2/

nPCSLOTE1

• Enable Card 1 for PC Card (PCMCIA or CF) in sin-

gle or dual card mode. This signal is used for gating

Input: PH2

other control signals to the appropriate PC Card.

• GPIO Port H

• Address Bit 9 for PC Card (CF) in single card mode

PH3/CFA9/ • Address Bit 25 for PC Card (PCMCIA) in single

T5 PCMCIAA25/ card mode

Input: PH3

nPCSLOTE2 • Enable Card 2 for PC Card (PCMCIA or CF) in

dual card mode. This signal is used for gating

other control signals to the appropriate PC Card.

R6

PH4/

nPCWAIT1

• GPIO Port H

• WAIT Signal for Card 1 for PC Card (PCMCIA or Input: PH4

CF) in single or dual card mode

• GPIO Port H

• Address Bit 10 for PC Card (CF) in single

PH5/CFA10/ card mode

R7 PCMCIAA24/ • Address Bit 24 for PC Card (PCMCIA) in single Input: PH5

nPCWAIT2

card mode

• WAIT Signal for Card 2 for PC Card (PCMCIA or

F) in dual card mode

P7

PH6/

• GPIO Port H

nAC97RESET • Audio Codec (AC97) Reset

Input: PH6

T6

PH7/

nPCSTATRE

• GPIO Port H

• Status Read Enable for PC Card (PCMCIA or F) Input: PH7

in single or dual card mode

T7 LCDFP

LCD Frame Synchronization pulse

LOW

R9 LCDLP

LCD Line Synchronization pulse

LOW

STANDBY

STATE

No Change

No Change

No Change

No Change

No Change

No Change

No Change

No Change

No Change

No Change

No Change

No Change

No Change

No Change

LOW

LOW

OUTPUT

DRIVE

I/O

NOTES

8 mA I/O

8 mA I/O

8 mA I/O

8 mA I/O

8 mA I/O

8 mA I/O

8 mA I/O

8 mA I/O

8 mA I/O

8 mA I/O

8 mA I/O

8 mA I/O

8 mA I/O

8 mA I/O

12 mA O

12 mA O

10

Rev. 02 — 19 March 2009

Product data sheet

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