LPC1102UK 데이터 시트보기 (PDF) - NXP Semiconductors.
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LPC1102UK Datasheet PDF : 43 Pages
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NXP Semiconductors
LPC1102/1104
32-bit ARM Cortex-M0 microcontroller
GPIO pins can be used as edge and level sensitive interrupt sources.
Four general purpose counter/timers with a total of one capture input and 10 match
outputs.
Programmable windowed WatchDog Timer (WDT).
Analog peripherals:
10-bit ADC with input multiplexing among five pins.
Serial interfaces:
UART with fractional baud rate generation, internal FIFO, and RS-485 support.
One SPI controller with SSP features and with FIFO and multi-protocol capabilities
(see Section 7.16).
Clock generation:
12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used
as a system clock.
Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from an external clock or the internal RC
oscillator.
Clock output function with divider that can reflect the system oscillator clock, IRC
clock, CPU clock, and the Watchdog clock (LPC1104 only).
Power control:
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep and Deep-sleep modes.
Power profiles residing in boot ROM allowing to optimize performance and
minimize power consumption for any given application through one simple function
call.
Two reduced power modes: Sleep and Deep-sleep modes.
Processor wake-up from Deep-sleep mode via a dedicated start logic using up to
six of the functional pins.
Power-On Reset (POR).
Brownout detect with up to four separate thresholds for interrupt and forced reset.
Unique device serial number for identification.
Single 3.3 V power supply (1.8 V to 3.6 V).
Available as WLCSP16 package.
3. Applications
Mobile devices
Consumer peripherals
Lighting
8-/16-bit applications
Portable devices
LPC1102_1104
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 26 September 2013
© NXP B.V. 2013. All rights reserved.
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