LPC1102UK 데이터 시트보기 (PDF) - NXP Semiconductors.
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LPC1102UK Datasheet PDF : 43 Pages
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NXP Semiconductors
LPC1102/1104
32-bit ARM Cortex-M0 microcontroller
4 GB
1 GB
0.5 GB
LPC1102/1104
reserved
private peripheral bus
reserved
AHB peripherals
reserved
APB peripherals
0xFFFF FFFF
0xE010 0000
0xE000 0000
0x5020 0000
0x5000 0000
0x4008 0000
0x4000 0000
reserved
reserved
16 kB boot ROM
reserved
0x2000 0000
0x1FFF 4000
0x1FFF 0000
8 kB SRAM
reserved
0x1000 2000
0x1000 0000
0 GB
32 kB on-chip flash
Fig 3. LPC1102/1104 memory map
0x0000 8000
0x0000 0000
AHB peripherals
0x5020 0000
127 - 16 reserved
15-12
11-8
7-4
3-0
reserved
reserved
GPIO PIO1
GPIO PIO0
0x5004 0000
0x5003 0000
0x5002 0000
0x5001 0000
0x5000 0000
APB peripherals
31 - 23 reserved
22
reserved
21 - 19 reserved
18
system control
17
IOCONFIG
16
SPI
15
flash controller
14
PMU
0x4008 0000
0x4005 C000
0x4005 8000
0x4004 C000
0x4004 8000
0x4004 4000
0x4004 0000
0x4003 C000
0x4003 8000
13 - 10 reserved
0x4002 8000
9
reserved
0x4002 4000
8
reserved
0x4002 0000
7
ADC
0x4001 C000
6
32-bit counter/timer 1 0x4001 8000
5
32-bit counter/timer 0 0x4001 4000
4
16-bit counter/timer 1 0x4001 0000
3
16-bit counter/timer 0 0x4000 C000
2
UART
0x4000 8000
1
WDT
0x4000 4000
0
reserved
0x4000 0000
0x0000 00C0
active interrupt vectors
0x0000 0000
002aaf526
7.5 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.5.1 Features
• Controls system exceptions and peripheral interrupts.
• In the LPC1102/1104, the NVIC supports 19 vectored interrupts including up to 6
inputs to the start logic from individual GPIO pins.
LPC1102_1104
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 26 September 2013
© NXP B.V. 2013. All rights reserved.
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