LPC2101 데이터 시트보기 (PDF) - Philips Electronics
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LPC2101 Datasheet PDF : 32 Pages
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Philips Semiconductors
LPC2101/2102/2103
Single-chip 16-bit/32-bit microcontrollers
6. Functional description
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective processor
core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM set.
• A 16-bit Thumb set.
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
The particular flash implementation in the LPC2101/2102/2103 allows for full speed
execution also in ARM mode. It is recommended to program performance critical and
short code sections in ARM mode. The impact on the overall code size will be minimal but
the speed can be increased by 30 % over Thumb mode.
6.2 On-chip flash program memory
The LPC2101/2102/2103 incorporate a 8 kB, 16 kB or 32 kB flash memory system
respectively. This memory may be used for both code and data storage. Programming of
the flash memory may be accomplished in several ways. It may be programmed In
System via the serial port. The application program may also erase and/or program the
flash while the application is running, allowing a great degree of flexibility for data storage
field firmware upgrades, etc. The entire flash memory is available for user code as the
bootloader resides in a separate memory.
The LPC2101/2102/2103 flash memory provides a minimum of 100,000 erase/write
cycles and 20 years of data-retention memory.
LPC2101_02_03_1
Preliminary data sheet
Rev. 01 — 18 January 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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