LPC2106BBD48(2003) 데이터 시트보기 (PDF) - Philips Electronics

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LPC2106BBD48
(Rev.:2003)

Single-chip 32-bit microcontrollers 128kB ISP/IAP FLASH with 64kB/32kB/16kB RAM

Philips Electronics 

Philips Semiconductors

CMOS single-chip 32-bit microcontroller

Data Sheet

LPC2104/2105/2106

FUNCTIONAL DESCRIPTION

Details of LPC2104, LPC2105 and LPC2106 systems and peripheral functions are described in the following sections.

Architectural Overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption.

The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity

results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor

core.

Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically,

while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to

high-volume applications with memory restrictions, or applications where code density is an issue.

The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two

instruction sets:

• The standard 32-bit ARM set.

• A 16-bit THUMB set.

The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of

the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB

code operates on the same 32-bit register set as ARM code.

THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM

processor connected to a 16-bit memory system.

On-Chip Flash Program Memory

The LPC2104, LPC2105 and LPC2106 incorporate a 128K byte Flash memory system. This memory may be used for both code

and data storage. Programming of the Flash memory may be accomplished in several ways. It may be programmed In System

via the serial port. The application program may also erase and/or program the Flash while the application is running, allowing a

great degree of flexibility for data storage field firmware upgrades, etc.

On-Chip static RAM

On-Chip static RAM memory may be used for code and/or data storage. The SRAM may be accessed as 8-bits, 16-bits, and 32-

bits. The LPC2106 provides a 64K byte static RAM, the LPC2105 provides a 32K byte static RAM while the LPC2104 provides

a 16K byte static RAM.

2003 Apr 10, 4:17 pm

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