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LS7566R

24-BIT x 4-AXES QUADRATURE COUNTER

LSI Corporation  

PR (x0PR, x1PR, x2PR, x3PR)

The PR is a 24-bit data register directly address-

able for write in individual segments of byte0 [PR0],

byte1 [PR1] and byte2 [PR2]. The PR serves as the in-

put portal for the counter (CNTR), since the CNTR is not

directly addressable for either read or write. In order to

preset the CNTR to any desired value the data is first

written into the PR and then transferred into the CNTR.

B23------------------------------------------------------------B0

PR: PR2

PR1

PR0

B7----------------B0 B7-------------B0 B7--------------B0

In mod-n and range-limit count modes the PR serves

as the repository for the division factor n and the count

range-limit, respectively. The PR can also be used to

hold the compare data for the CNTR wherein the equal-

ity PR = CNTR sets an output flag.

CNTR (x0CNTR, x1CNTR, x2CNTR, x3CNTR):

The CNTR is a 24-bit up/down counter which counts the

up/down pulses resulting from tthe quadrature clocks ap-

plied at A and B inputs or alternatively, in non-

quadrature mode, pulses applied at the A input. The

CNTR is not directly accessible for read or write; instead

it can be preloaded with data from the PR or it can port

its own data out to the OL which in turn can be accessed

by read operation. In both quadrature and non-

quadrature modes, the CNTR can be further configured

into either free-running or single-cycle or mod-n or

range-limit mode.

OL (x0OL, x1OL, x2OL, x3OL):

The OL is a 24-bit register directly addressable for read

in individual segments of byte0 [OL1], byte1 [OL1] and

byte2 [OL2]. OL serves as the output portal for the

CNTR. Snapshot of the CNTR data can be loaded in the

OL without interfering with the counting process, which

then can be accessed by read.

B23-----------------------------------------------------------B0

OL: OL2

OL1

OL0

STR (x0STR, x1STR, x2STR, x3STR):

The STR is an 8-bit status register indicating count related

status.

STR: CY BW CMP IDX CEN 0 U/D S

B7 B6 B5 B4 B3 B2 B1 B0

An individual STR bit is set to 1 when the bit related event

has taken place. The STR is cleared to 0 at power-up. The

STR can also be cleared through the control register CMR

with the exception of bit1 (U/D) and bit3 (CEN). These two

STR bits always indicate the instantaneous status of the

count_direction and count_enable assertion/de-assertion.

The STR bits are described below:

B7 (CY): Carry; set by CNTR overflow

B6 (BW): Borrow; set by CNTR underflow

B5 (CMP): Set when CNTR = PR

B4 (IDX): Set when INDX input is at active level

B3 (CEN): Set when counting is enabled, reset when

counting is disabled

B2 (0): Always 0

B1 (U/D): Set when counting up, reset when counting

down

B0 (S): Sign of count value; set when negative, reset

when positive

IMR:

The IMR is a trans-axis global register used for masking out

the interrupt function of individual axes. It is a 4-bit read/write

register with the following bit assignments.

IMR: B3 B2 B1 B0

B0 = 0: disable axis 0 interrupt

= 1: enable axis 0 interrupt

B1 = 0: disable axis 1 interrupt

= 1: enable axis 1 interrupt

B2 = 0: disable axis 2 interrupt

= 1: enable axis 2 interrupt

B3 = 0: disable axis 3 interrupt

= 1: enable axis 3 interrupt

B7----------------B0 B7-------------B0 B7--------------B0

A write to IMR places the lower nibble of the databus into the

IMR with identical bit map. A read of IMR produces a joint

read of IMR and ISR (interrupt status register), with IMR oc-

cupying the lower nibble and ISR occupying the upper nibble

of the databus.

7566R-121405-2

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