LS7566R 데이터 시트보기 (PDF) - LSI Corporation
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LS7566R Datasheet PDF : 13 Pages
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For VDD = 3.3V ±10%
Parameter
Quadrature Mode (See Fig. 4-6)
PCK High Pulse Width
PCK Low Pulse Width
PCK Frequency
Filter Clock(ff)Period
Symbol
t1
t2
fPCK
t3
t3
Min. Value
24
24
-
50
100
Max.Value Unit
-
ns
-
ns
20
MHz
-
ns
-
ns
Filter clock frequency
ff
Quadrature Separation
t4
Quadrature Clock Pulse Width
t5
Quadrature Clock frequency
fQA, fQB
Quadrature Clock to Count Delay
tQ1
X1/X2/X4 Count Clock Pulse Width tQ2
Quadrature Clock to
FLGa delay
tfda
Quadrature Clock to
FLGb delay
tfdb
FLGa to INT/ delay
tnt
INDX/ Input Pulse Width (Synchronous) tid
INDX/ set-up time (Synchronous)
tis
INDX/ hold time (Synchronous)
tih
FLGa Output Width
tfw
-
52
105
-
4t3
25
4.5t3
3t3
0
60
10
10
50
20
-
-
4.5
5t3
-
5.5t3
4t3
-
-
-
-
-
MHz
ns
ns
MHz
-
ns
ns
ns
ns
ns
ns
ns
ns
Non-Quadrature Mode (See Fig. 7-8)
Clock A - High Pulse Width
t6
Clock A - Low Pulse Width
t7
Direction Input B Set-up Time
t8s
Direction Input B Hold Time
t8
Clock Frequency
fA
Clock to FLGa Out Delay
t9
FLGa Out Pulse Width
t10
INDX/ Pulse Width (Asynchronous) t11
For VDD = 5V ±10%
Parameter
Quadrature Mode (See Fig. 4-6)
PCK High Pulse Width
PCK Low Pulse Width
PCK Frequency
Filter Clock(ff)Period
Symbol
t1
t2
fpCK
t3
t3
24
-
ns
24
-
ns
24
-
ns
20
-
ns
-
20
MHz
-
40
ns
24
-
ns
30
-
ns
Min. Value
12
12
-
25
50
Max.Value Unit
-
ns
-
ns
40
MHz
-
ns
-
ns
Filter clock frequency
ff
Quadrature Separation
t4
Quadrature Clock Pulse Width
t5
Quadrature Clock frequency
fQA, fQB
Quadrature Clock to Count Delay
tQ1
x1 / x2 / x4 Count Clock Pulse Width tQ2
Quadrature Clock to
FLGa delay
tfda
Quadrature Clock to
FLGb delay
tfdb
FLGa to INT/ delay
tnt
INDX/ Input Pulse Width (Synchronous) tid
INDX/ set-up time (Synchronous)
tis
INDX/ hold time (Synchronous)
tih
FLGa Output Width
tfw
-
26
52
-
4t3
12
4.5t3
3t3
0
32
5
5
24
40
-
-
9.6
5t3
-
5.5t3
4t3
-
-
-
-
-
MHz
ns
ns
MHz
-
ns
ns
ns
ns
ns
ns
ns
ns
Non-Quadrature Mode (See Fig. 7-8)
Clock A - High Pulse Width
t6
12
Clock A - Low Pulse Width
t7
12
Direction Input B Set-up Time
t8
12
Direction Input B Hold Time
t8
10
Clock Frequency
fA
-
Clock to FLGa Out Delay
t9
-
FLGa Out Pulse Width
t10
12
INDX/ Pulse Width (Asynchronous) t11
15
-
ns
-
ns
-
ns
-
ns
40
MHz
20
ns
-
ns
-
ns
7566R-121605-8
Remarks
-
-
-
t3 = t1+ t2, MDR0 <7> =0
t3 = t1+ t2, MDR0 <7> =1
ff = 1/ t3
t4 > t3
t5 > 2t3
fQA = fQB < 1/4t3
-
tQ2 = t3/2
-
-
-
tid > t4
-
-
tfw ≈ t4
-
-
-
-
fA = ( 1/ (t6 + t7) )
-
t10 = t7
-
Remarks
-
-
-
t3 = t1+ t2, MDR0 <7> =0
t3 = t1+ t2, MDR0 <7> =1
-
t4 > t3
t5 > 2t3
fQA = fQB < 1/4t3
-
tQ2 = t3/2
-
-
-
tid > t4
-
-
tfw ≈ t4
-
-
-
-
fA = ( 1/ (t6 + t7) )
-
t10 = t7
-
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