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LT1310 데이터 시트보기 (PDF) - Linear Technology

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LT1310 Datasheet PDF : 12 Pages
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LT1310
APPLICATIO S I FOR ATIO
Layout Hints
The high speed operation of the LT1310 demands careful
attention to board layout. You will not get advertised
performance with careless layout. Figure 6 shows the
recommended component placement for a boost
converter.
CC RC
R1
R2 CT
VIN
CIN
SHDN
LT1310
L1
SYNC
RLP
CLP
COUT
SW
MULTIPLE VIAS
D1
GND
VOUT
1310 F06
Figure 6. Recommended Component Placement for Boost Converter. Note Direct High Current Paths Using Wide PC Traces. Minimize
Trace Area at Pin 10 (VC), Pin 9 (CT) and Pin 1 (FB). Use Multiple Vias to Tie Pin 5 Copper and the Exposed Pad to Ground Plane. Use
Vias at One Location Only to Avoid Introducing Switching Currents Into the Ground Plane
PACKAGE DESCRIPTIO
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1663)
0.254
(.010)
GAUGE PLANE
DETAIL “A”
0° – 6° TYP
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
10 9 8 7 6
0.497 ± 0.076
(.0196 ± .003)
REF
4.90 ± 0.15
(1.93 ± .006)
3.00 ± 0.102
(.118 ± .004)
NOTE 4
12345
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.06 ± 0.102
1
(.081 ± .004)
1.83 ± 0.102
(.072 ± .004)
10
0.53 ± 0.01
(.021 ± .006)
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE 0.17 – 0.27
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
(.007 – .011)
TYP
0.50
(.0197)
BSC
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.86
(.034)
REF
2.794 ± 0.102
(.110 ± .004)
0.889 ± 0.127
(.035 ± .005)
0.13 ± 0.076
(.005 ± .003)
5.23
(.206)
MIN
2.083 ± 0.102 3.2 – 3.45
(.082 ± .004) (.126 – .136)
MSOP (MSE) 0802
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
RECOMMENDED SOLDER PAD LAYOUT
sn1310 1310fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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