CMM1530-LC 데이터 시트보기 (PDF) - Celeritek, Inc.
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CMM1530-LC Datasheet PDF : 4 Pages
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CMM1530-LC
Advanced Product Information - November 2002
(2 of 4)
Electrical Characteristics
Unless otherwise specified, the following specifications are guaranteed at room temperature with drain voltage (+Vd) = 3.5 V in Celeritek test fixture.
Parameter
Condition
Min
Typ
Max
Units
Frequency Range
1.85
1.91 GHz
Gain
@ Digital power output
28
31
dB
Gain Ripple*
1805-1880 MHz & 1850-1910 MHz
1.5
dB
Gain Variation
Over supply voltage
2
dB/V
Over temperature
0.03
dB/°C
Power Output Control Range Vdd = 0 V to +3.5 V
50
dB
Power Output
Meets IS-136 TDMA mask
+30.0
dBm
Meets IS-98 CDMA mask
+28.5
dBm
Harmonics
2nd @ Digital power output, no output trapping, Po=+28.5 dBm
-30
dBc
3rd @ Digital power output, no output trapping, Po=+28.5 dBm
-40
dBc
Noise Power in Receive Band 30 kHz bandwidth
-94
dBm
Linearity
CDMA modulation @ +28.5 dBm Pout, 1.25 MHz offset -45
dBc/30KHz
TDMA modulation @ +30 dBm Pout - Adjacent
-26
dBc
TDMA modulation @ +30 dBm Pout - Alternate
-45
dBc
Spurious Signal
VSWR = 3:1 in-band, VSWR = 10:1 out-of-band
-80
dBc
Noise Figure
3.0
dB
Input Return Loss
10
dB
Output Return Loss
8
dB
Efficiency (Vdd = 3.0 V)
Pout = +30.0 dBm - TDMA
36
38
%
Pout = +28.5 dBm - CDMA
32
35
%
Positive Supply Current (Id)
Pout IS-136 TDMA
Pout IS-98 CDMA
750
mA
595
mA
Quiescent Current (Iq)
No RF CDMA mode
No RF TDMA mode
130
mA
200
mA
Negative Supply Current (-Ig) Includes external resistor divider
Negative Supply Voltage (-Vg) Into external resistor divider
1.1
2.0
mA
-0.5
-0.8
-1.4
V
* Specifications guaranteed over the temperature range of -20°C to +80°C
– Continued from Page 1 –
It is very important to provide adequate de-coupling
between the RF and DC signals in designing the DC bias cir-
cuit. Inadequate by-pass capacitance and inductance around the
DC supply lines can compromise the adjacent channel power
ratio (ACPR), or reduce power gain and/or create oscillations.
The recommend DC by-pass capacitance and low-pass in-line
inductance are shown in the evaluation board on Page 4.
Matching Circuits Output matching and input matching cir-
cuits are required to achieve the RF specifications in this data
sheet. The recommend matching circuits are identical to the
matching circuits for the evaluation board shown on Page 4.
For output power matching, one shunt capacitor along the
transmission line connected to Pins 6 and 7 as well as the bond
wire inside the package from the output leads to the output
FET are used to transform 50Ω impedance to the load line
resistance of the output FET. The placement and the value of
the capacitor are important in achieving the performance
desired. Matching circuits for the frequencies other than the
one shown can be achieved by changing the capacitor value
and the placement position of the capacitor. The device can be
designed to work from UHF to around 3 GHz.
Supply Ramping To obtain power ramping, gate supply con-
trol is recommend. Drain supply voltage ramping can also be
used.
Modulation When biased as specified, the CMM1530-LC
will achieve the required adjacent channel response for the
digital PCS system specified. Celeritek tests each product
under digital modulation to ensure correlation to customer
applications.
Thermal
1. The copper pad on the backside of the CMM1530-LC must
be soldered to the ground plane.
2. All 8 leads of the package must be soldered to the appropri-
ate electrical connection.
Typical Performance
Wideband Gain & Return Loss
vs Frequency @ 3.5 V, +25°C
35
30
25
20
0.5
Gain
Output Return Loss
Input Return Loss
1.0
1.5
2.0
2.5
Frequency, GHz
0
-10
-20
-30
-40
3.0
3236 Scott Boulevard, Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
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