LT1640 데이터 시트보기 (PDF) - Linear Technology
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LT1640 Datasheet PDF : 12 Pages
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LT1640L/LT1640H
APPLICATIONS INFORMATION
GND
LT1640H
R4
3
UV
+
R5
+– VPG
2
OV
–
R6
VEE SENSE
4
5
8
VDD
PWRGD 1
R7
+
5k
Q2
Q3
VEE DRAIN 7
GATE
6
R3
C1 R2
C2
ACTIVE LOW
ENABLE MODULE
VIN+ VOUT+
ON/OFF
C3
VIN– VOUT–
R1
– 48V
Q1
1640 F11
Figure 11. Active High Enable Module
GND
LT1640L
R4
3
UV
+
R5
2
+– VPG –
OV
R6
VEE SENSE
4
5
8
VDD PWRGD 1
+
Q2
VEE
DRAIN 7
GATE
6
R3
C1 R2
C2
ACTIVE LOW
ENABLE MODULE
VIN+ VOUT+
ON/OFF
C3
VIN– VOUT–
– 48V
R1
Q1
1640 F12
Figure 12. Active Low Enable Module
pull-up current in the module then flows through R7,
pulling the PWRGD pin high and enabling the module.
When the DRAIN voltage of the LT1640L is high with
respect to VEE, the internal pull-down transistor Q2 is off
and the PWRGD pin is in a high impedance state (Figure
12). The PWRGD pin will be pulled high by the module’s
internal pull-up current source, turning the module off.
When the DRAIN voltage drops below VPG, Q2 will turn on
and the PWRGD pin will pull low, enabling the module.
The PWRGD signal can also be used to turn on an LED or
optoisolator to indicate that the power is good as shown in
Figure 13.
Gate Pin Voltage Regulation
When the supply voltage to the chip is more than 15.5V,
the GATE pin voltage is regulated at 13.5V above VEE. If the
supply voltage is less than 15.5V, the GATE voltage will be
about 2V below the supply voltage. At the minimum 10V
supply voltage, the gate voltage is guaranteed to be greater
than 6V. The gate voltage will be no greater than 18V for
supply voltages up to 80V.
GND
R4
562k
1%
R5
9.09k
1%
R6
10k
1%
– 48V
3
UV
2
OV
VEE
4
SENSE
5
R1
0.02Ω
5%
8
VDD
LT1640L
1
PWRGD
GATE
DRAIN
C1
0.033µF
24V
6
7
R2 R3
10Ω 10k C2
5% 5% 3.3nF
100V
Q1
IRF530
R7
51k
5%
4N25
Figure 13. Using PWRGD to Drive an Optoisolator
PWRGD
+ C3
100µF
100V
1640 F13
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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