1719 데이터 시트보기 (PDF) - Linear Technology
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1719 Datasheet PDF : 16 Pages
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LT1719
APPLICATIONS INFORMATION
5V
180Ω
LSTTL 270Ω
5V
10KH/E
DO NOT USE FOR LT1719
LEVEL TRANSLATION. SEE TEXT
820Ω
(a) STANDARD TTL TO PECL TRANSLATOR
VCC
+ VS
LT1719
R2
R1
R3
VEE
(b) LT1719 OUTPUT TO PECL TRANSLATOR
VCC 3V
VECL
LT1719
R2
R1
R4
R3
VEE
(c) 3V LT1719 OUTPUT TO PECL TRANSLATOR
VCC +VS
+ VS
R1 R2 R3
10KH/E 5V OR 5.2V 510Ω 180Ω 750Ω
100K/E 4.5V 620Ω 180Ω 510Ω
VECL
R1 R2 R3 R4
10KH/E 5V OR 5.2V 300Ω 180Ω OMIT 560Ω
100K/E 4.5V 330Ω 180Ω 1500Ω 1000Ω
LT1719
R4
R1
R2 R3
VEE
VECL
(d) LT1719 OUTPUT TO STANDARD ECL TRANSLATOR
ECL FAMILY VECL + VS R1 R2 R3 R4
10KH/E
– 5.2V 5V 560Ω 270Ω 330Ω 1200Ω
3V 270Ω 510Ω 300Ω 330Ω
100K/E
– 4.5V 5V 680Ω 270Ω 300Ω 1500Ω
3V 330Ω 390Ω 270Ω 430Ω
1719 F06
Figure 6
evaluated carefully. Note that there is some degradation of
noise margin due to the ±5% resistor selections shown.
With 10KH/E, there is no temperature compensation of the
logic levels, whereas the LT1719 and the circuits shown
give levels that are stable with temperature. This will lower
the noise margin over temperature. In some configura-
tions it is possible to add compensation with diode or
transistor junctions in series with the resistors of these
networks.
For more information on ECL design, refer to the ECLiPS
data book (DL140), the 10KH system design handbook
(HB205) and PECL design (AN1406), all from Motorola.
Circuit Description
The block diagram of the LT1719 is shown in Figure 7. The
circuit topology consists of a differential input stage, a
gain stage with hysteresis and a complementary com-
mon-emitter output stage. All of the internal signal paths
utilize low voltage swings for high speed at low power.
The input stage topology maximizes the input dynamic
range available without requiring the power, complexity
and die area of two complete input stages such as are
found in rail-to-rail input comparators. With a single 2.7V
supply, the LT1719 still has a respectable 1.6V of input
11
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